AD9882SLASHPCB datasheet(24/36 Pages) AD

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REV. A

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AD9882

Table IX. Control Register Map (continued)

Hex

Read and Write

Default

Address

or Read Only

Bit

Value

Function

R/W

**** ***0Enable 4:2:2

0 = 4:4:4 mode

1 = 4:2:2 mode

Analog Hsync Active

0 = Hsync not detected

1 = Hsync detected

6Analog SOG Active

0 = Sync signal not detected on green channel

1 = Sync signal detected on green channel

5Analog Vsync Active

0 = Vsync not detected

1 = Vsync detected

DVI Active

0 = Digital interface clock not detected

1 = Digital interface clock detected

3Active Interface

0 = Analog interface active

1 = DVI interface active

Active Hsync

0 = Hsync from the Hsync input pin

1 = Hsync from the SOG input

6Hsync Polarity Detected

0 = Active low polarity detected

1 = Active high polarity detected

5Active Vsync

0 = Vsync from the Vsync input pin

1 = Vsync from SOG

4Vsync Polarity Detected

0 = Active high polarity detected

1 = Active low polarity detected

3Coast Polarity Detected

0 = Active low polarity detected

1 = Active high polarity detected

This function works only with internal coast.

HDCP Keys Detected

0 = Not detected

1 = Detected

R/W

7–0

0000 0000

Test Register

Must be set to 1000 0000 for proper operation.

R/W

7–0

0000 000X

Test Register

Must be set to 1100 000x for proper operation.

R/W

7–0

0000 010X

Test Register

Must be set to 0111 110x for proper operation.

R/W

7–0

0011 1111

Test Register

Must be set to default for proper operation.

R/W

*** ****

MDA and MCL

0 = MDA and MCL three-stated

1 = MDA and MCL not three-stated

6–0

*111 0000

Test Register

Must be set to

*110 0111 for proper operation.

R/W

7–0

0000 1111

Test Register

Must be set to default for proper operation.

7–0Test Register

Reserved for future use.

7–0Test Register

Reserved for future use.

AD9882/PCB 数据表(PDF) 24 Page - Analog Devices

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AD9882/PCB 数据表(PDF) 24 Page - Analog Devices

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