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ADE7751ARSRL 数据表(PDF) 14 Page - Analog Devices |
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ADE7751ARSRL 数据表(HTML) 14 Page - Analog Devices |
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14 / 16 page ![]() REV. 0 ADE7751 –14– V1B < 87.5% OF V1A 0V V1A V1B V1A V1A V1N AGND V1B V1B FILTER AND COMPARE TO MULTIPLIER FAULT A B Figure 13. Fault Conditions for Inactive Input Less than Active Input Fault with V1B Greater than V1A Figure 14 illustrates another fault condition. If V1A is the active input (i.e., is being used for billing) and the voltage signal on V1B (inactive input) becomes greater than 114% of V1A, the FAULT indicator goes active, and there is also a swap over to the V1B input. The analog input V1B has now become the active input. Again there is a time delay of about 1.2 seconds associated with this swap. V1A will not swap back to being the active channel until V1A becomes greater than 114% of V1B. However, the FAULT indicator will become inactive as soon as V1A is within 12.5% of V1B. This threshold eliminates poten- tial chatter between V1A and V1B. V1A < 87.5% OF V1B OR V1B > 114% OF V1A 0V V1A V1B V1A V1A V1N AGND V1B V1B FILTER AND COMPARE TO MULTIPLIER FAULT A B Figure 14. Fault Conditions for Inactive Input Greater than Active Input Calibration Concerns Typically, when a meter is being calibrated, the voltage and current circuits are separated as shown in Figure 15. This means that current will only pass through the phase or neutral circuit. Figure 15 shows current being passed through the phase circuit. This is the preferred option since the ADE7751 starts billing on the input V1A on power-up. The phase circuit CT is connected to V1A in the diagram. Since there is no current in the neutral circuit, the FAULT indicator will come on under these conditions. However, this does not affect the accuracy of the calibration and can be used as a means to test the functionality of the fault detection. If the neutral circuit is chosen for the current circuit in the arrangement shown in Figure 15, it may have implications for the calibration accuracy. The ADE7751 will power up with the V1A input active as normal. However, since there is no current in the phase circuit, the signal on V1A is zero. This will cause a FAULT to be flagged and the active input to be swapped to V1B (Neutral). The meter may be calibrated in this mode, but the phase and neutral CTs may differ slightly. Since under no-fault conditions all billing is carried out using the phase CT, the meter should be calibrated using the phase circuit. Of course, both phase and neutral circuits may be calibrated. Ib V 240Vrms NOTE Ra Rf; Rb + VR = Rf Rb Rb V1A 0V V1B CT V1A AGND Rf CT NEUTRAL PHASE V1N Cf Cf Rf Rb VR V2P Rf V2N Cf Cf TEST CURRENT Ib Ra Figure 15. Fault Conditions for Inactive Input Greater than Active Input TRANSFER FUNCTION Frequency Outputs F1 and F2 The ADE7751 calculates the product of two voltage signals (on Channel 1 and Channel 2) and then low-pass filters this product to extract real power information. This real power information is then converted to a frequency. The frequency information is output on F1 and F2 in the form of active low pulses. The pulse rate at these outputs is relatively low, e.g., 0.34 Hz maximum for ac signals with S0 = S1 = 0 (see Table III). This means that the frequency at these outputs is generated from real power informa- tion accumulated over a relatively long period of time. The result is an output frequency that is proportional to the average real power. The averaging of the real power signal is implicit to the digital-to-frequency conversion. The output frequency or pulse rate is related to the input voltage signals by the following equation. Freq VV Gain F VREF = ×× × × 574 1 2 14 2 . – (7) where, Freq =Output frequency on F1 and F2 (Hz) V1= Differential rms voltage signal on Channel 1 (Volts) V2= Differential rms voltage signal on Channel 2 (Volts) Gain = 1, 2, 8, or 16, depending on the PGA gain selection made using logic inputs G0 and G1 VREF =The reference voltage (2.5 V ± 8%) (Volts) F1–4 =One of four possible frequencies selected by using the logic inputs S0 and S1 (see Table II) Table II. S1 S0 F1–4 (Hz) XTAL/CLKIN * 00 1.7 3.579 MHz/2 21 01 3.4 3.579 MHz/2 20 10 6.8 3.579 MHz/2 19 11 13.6 3.579 MHz/2 18 *F1–4 are a binary fraction of the master clock and will thus vary if the specified CLKIN frequency is altered. |
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