ADM8840

REV. PrG

2/03

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Analog Devices, Inc., 200

3

Charge Pump Regulator & COM Driver

for Color TFT Panel

Preliminary Technical Data

PRELIMINARY TECHNICAL DATA

a

FEATURES

Programmable COM Driver to prevent Screen-Burn

3 Voltages (5.0V,15.0V,-15.0V) from one 3V Supply

Power Efficiency optimised for use with TFT in mobile

phones

Low Quiescent Current

Low Shutdown Current (<5uA)

Shutdown Function

APPLICATIONS

Handheld Instruments

TFT LCD Panels

Cellular Phones

GENERAL DESCRIPTION

The ADM8840 combines a charge pump regulator and a

Common Line (COM) driver in a single chip solution for use

in TFT LCD’s. The device provides an LCD controller and

grayscale DAC supply voltage of 5.0V (±2%), 2 gate drive

voltages of +15V and -15V and a COM driver voltage. This

COM Driver voltage alternates the polarity of the Common

line voltage every line (or every frame) on the display in order

to prevent screen-burn occuring over time. The ADM8840

is powered by a single 3.0V supply.

The ADM8840 has an internal 100KHz oscillator for driving

the charge pumps.

The COM Driver section of the ADM8840 can be used to

generate the alternate frame or line inversion of the COM

line of the LCD panel.

The ADM8840 receives the COM

clock from the controller with a frequency up to 10kHz and

allows programmable conditioning of its amplitude and

centre voltage through the use of on-board DAC’s. This

allows programmable elimination of display flicker caused

by the COM inversion.

The COM_OUT amplitude can be programmed from 4.0V

to 7.0V in steps of 28mV. The COM_OUT centre voltage

can be programmed to 0.9V to 2.8V in steps of 14mV.

The ADM8840 provides power up sequencing of the -15V

and +15V gate drive outputs, ensuring the -15V starts to

power up before the +15V.

The ADM8840 has a number of power save features, includ-

ing low power Shutdown. The 5.0V output consumes the

most power, so Power Efficiency is also maximised on this

output with an oscillator enabling scheme (Green Idle

The ADM8840 is fabricated using CMOS technology for

minimal power consumption.

The part is packaged in a 32-

pin LFCSP package.

FUNCTIONAL BLOCK DIAGRAM

SERIAL

INTERFACE

VREF

DAC 1

DAC 2

8

8

CLK

DATA

LEVEL

TRANSLATOR

PO WER

BUFFER

+

-

-

+

COM_IN

4.7 F

4.7 F

5.5k

4.7 F

OS CILLATOR

CONTROL

LOGIC

TIMING

GENERATOR

SHUTDOWN

CONTROL

DISCHARGE

VOLTAGE

DOUBLER

C1+

C1-

SHDN

VCC

LDO

VOLTAGE

REGULATOR

5VOUT

2.2 F

C7

DOUBLE

TRIP LE

VOLTAGE

TRIPLER

VOLTAGE

INVERTER

C2+

C2-

C3+

C3-

VOUT

VOLTAGE

ADDER

C5+

C5-

+15V

C4+

C4-

-15V

ADM8840

0.22 F

3.3 F

3.3 F

3.3 F

0.22 F

0.22 F

0.22 F

0.22 F

DAC1_SD

DAC1_IN

INT/EXT

DAC 1

INT/EXT

DAC 2

DAC2_SD

DAC2_IN

C4

C2

C3

C9

C8

ADD_OUT

TRANS_OUT

COM_OUT_AC

COM_OUT

GND

C5

C10

C11

C12

C13

4.7 F

C6

C1

22nF

5VIN

+5V