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ADS5500IPAPR 数据表(PDF) 5 Page - Texas Instruments

部件名 ADS5500IPAPR
功能描述  14BIT, 125MSPS ANALOG-TO-DIGITAL CONVERTER
PDF  29 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

ADS5500IPAPR 数据表(HTML) 5 Page - Texas Instruments

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ADS5500
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
www.ti.com
5
ELECTRICAL CHARACTERISTICS (continued)
Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 125MSPS, 50% clock duty
cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
PARAMETER
UNIT
MAX
TYP
MIN
CONDITIONS
Effective number of bits, ENOB
fIN = 70MHz
11.3
Bits
f = 10.1MHz, 15.1MHz
(−7dBFS each tone)
85
dBc
Two-tone intermodulation distortion, IMD
f = 30.1MHz, 35.1MHz
(−7dBFS each tone)
85
dBc
f = 50.1MHz, 55.1MHz
(−7dBFS each tone)
88
dBc
Power Supply
Total supply current, ICC
VIN = full-scale, fIN = 55MHz
AVDD = DRVDD = 3.3V
236
265
mA
Analog supply current, IAVDD
VIN = full-scale, fIN = 55MHz
AVDD = DRVDD = 3.3V
175
190
mA
Output buffer supply current, IDRVDD
VIN = full-scale, fIN = 55MHz
AVDD = DRVDD = 3.3V
61
75
mA
Analog only
578
627
mW
Power dissipation
Total power with 10pF load on
digital output to ground
780
875
mW
Standby power
With clocks running
181
250
mW
DIGITAL CHARACTERISTICS
Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 125MSPS, 50% clock duty
cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
10
µA
Low-level input current
10
µA
Input current for RESET
−20
µA
Input capacitance
4
pF
Digital Outputs(1)
Low-level output voltage
CLOAD = 10pF(2), fS = 125MSPS
0.3
V
High-level output voltage
CLOAD = 10pF(2), fS = 125MSPS
3.0
V
Output capacitance
3
pF
(1) For optimal performance, all digital output lines (D0:D13), including the output clock, should see a similar load.
(2) Equivalent capacitance to ground of (load + parasitics of transmission lines).



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