ADR01/ADR02/ADR03/ADR06

Rev. F | Page 18 of 20

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-203AA

2.00 BSC

0.30

0.15

0.10 MAX

1.00

0.90

0.70

SEATING

PLANE

1.10 MAX

0.22

0.08

0.46

0.36

0.26

4

PIN 1

2.10 BSC

0.65 BSC

1.25 BSC

0.10 COPLANARITY

Figure 45. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-5)

Dimensions shown in millimeters

PIN 1

1.60 BSC

2.80 BSC

1.90

BSC

0.95 BSC

13

4

5

2

0.20

0.08

0.60

0.45

0.30

8°

4°

0.50

0.30

0.10 MAX

SEATING

PLANE

1.00 MAX

0.90

0.87

0.84

COMPLIANT TO JEDEC STANDARDS MO-193AB

2.90 BSC

Figure 46. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions shown in millimeters

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099)

× 45°

8°

0°

1.75 (0.0688)

1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0040)

4

1

85

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)

BSC

6.20 (0.2440)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012AA

Figure 47. 8-Lead Standard Small Outline Package [SOIC]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)