DP83902AVF datasheet(4/70 Pages) NSC

4 / 70 page

Connection Diagrams (Continued)

TLF11157 – 65

Order Number DP83902AVJG

See NS Package Number VJG100A

20 Pin Description

PQFP

PLCC

AVJG

Description

Pin No

Name

BUS INTERFACE PINS

INT

INTERRUPT

Indicates that the DP83902A requires CPU attention after

reception transmission or completion of DMA transfers The interrupt is cleared

by writing to the ISR (Interrupt Status Register) All interrupts are maskable

WACK

WRITE ACKNOWLEDGE

Issued from system to DP83902A to indicate that

data has been written to the external latch The DP83902A will begin a write

cycle to place the data in local memory

PRD

PORT READ

Enables data from external latch on to local bus during a

memory write cycle to local memory (remote write operation) This allows

asynchronous transfer of data from the system memory to local memory

99 100

8 – 11

RA3 – RA0

These four pins are used to select a register to be read

1 2

98 – 100

or written The state of these inputs is ignored when the DP83902A is not in

slave mode (CS high)

DP83902AVF 数据表(PDF) 4 Page - National Semiconductor (TI)

DP83902AVF 数据表(HTML) 4 Page - National Semiconductor (TI)

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