DP83916 datasheet(48/96 Pages) NSC

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50 Bus Interface (Continued)

TABLE 5-1 Pin Description

(Continued)

Symbol

Driver

Direction

Description

Type

BUS INTERFACE PINS

(Continued)

A31 – A1

TRI

O Z

Address Bus

These signals are used by the SONIC-16 to drive the DMA address after

the SONIC-16 has acquired the bus Since the SONIC-16 aligns data to word

boundaries only 23 address lines are needed

RA5 – RA0

These signals are used to access SONIC-16’s internal

registers When the SONIC-16 is accessed the CPU drives these lines to select the

desired SONIC-16 register

TRI

I O Z

Address Strobe (AS)

When BMODE e 1 the falling edge indicates valid status and

address The rising edge indicates the termination of the memory cycle

ADS

TRI

O Z

Address Strobe (ADS)

When BMODE e 0 the rising edge indicates valid status and

address

MRW

TRI

O Z

When the SONIC-16 has acquired the bus this signal indicates the direction of data

MWR

TRI

O Z

Memory ReadWrite Strobe (MRW)

When BMODE e 1 this signal is high during a

read cycle and low during a write cycle

Memory ReadWrite Strobe (MWR)

When BMODE e 0 the signal is low during a

read cycle and high during a write cycle

INT

O Z

Indicates that an interrupt (if enabled) is pending from one of the sources indicated by

the Interrupt Status register Interrupts that are disabled in the Interrupt Mask register

INT

will not activate this signal

Interrupt (INT)

This signal is active low when BMODE e 1

Interrupt (INT)

This signal is active high when BMODE e 0

RESET

Reset

This signal is used to hardware reset the SONIC-16 When asserted low the

SONIC-16 transitions into the reset state after 10 transmit clocks or 10 bus clocks if the

bus clock period is greater than the transmit clock period

S2–S0

Bus Status

These three signals provide a continuous status of the current SONIC-16

bus operations See Section 543 for status definitions

BSCK

Bus Clock

This clock provides the timing for the SONIC-16 DMA engine

O Z

Bus Request (BR)

When BMODE e 1 the SONIC-16 asserts this pin low when it

attempts to gain access to the bus When inactive this signal is at TRI-STATE

HOLD

Hold Request (HOLD)

When BMODE e 0 the SONIC-16 drives this pin high when it

intends to use the bus and is driven low when inactive

Bus Grant (BG)

When BMODE e 1 this signal is a bus grant The system asserts this

pin low to indicate potential mastership of the bus

HLDA

Hold Acknowledge (HLDA)

When BMODE e 0 this signal is used to inform the

SONIC-16 that it has attained the bus When the system asserts this pin high the

SONIC-16 has gained ownership of the bus

BGACK

TRI

I O Z

Bus Grant Acknowledge

When BMODE e 1 the SONIC-16 asserts this pin low when

it has determined that it can gain ownership of the bus The SONIC-16 checks the

following signal before driving BGACK 1)BG has been received through the bus

arbitration process 2) AS is deasserted indicating that the CPU has finished using the

bus 3) DSACK0 and DSACK1 are deasserted indicating that the previous slave device

is off the bus 4) BGACK is deasserted indicating that the previous master is off the bus

This pin is only used when BMODE e 1

DP83916 数据表(PDF) 48 Page - National Semiconductor (TI)

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