CPC5622

R03

www.ixysic.com

13

Figure 5. Differential and Single-ended Transmit

Path Connections to LITELINK

3.4 Initialization Requirement

Following Power-up

OH must be de-asserted (set logic high) once after

power-up for at least 50ms to transfer internal gain

trim values within LITELINK. This would be normal

operation in most applications. Failure to comply with

this requirement will result in transmission gain errors

and possibly distortion.

3.5 DC Characteristics

The CPC5622 is designed for worldwide applications.

Modification of the values of the components at the

ZDC, DCS1, and DCS2 pins allow for control of the VI

slope characteristics of LITELINK. Selecting

enable compliance with various DC requirements.

3.5.1 Setting a Current Limit

LITELINK includes a telephone line current limit

feature that is selectable by choosing the desired

IXYS Integrated Circuits Division recommends using

8.2

 for R

telephone line current to 130 mA.

Whether using the recommended value above or

refer to the guidelines for FET thermal management

provided in AN-146, Guidelines for Effective

LITELINK Designs.

3.6 AC Characteristics

3.6.1 Resistive Termination Applications

North American and Japanese telephone line AC

termination requirements are met with a resistive

600

 ac 2-wire termination. For these applications

LITELINK’s 2-wire network termination impedance is

pin 29, with a value of 301

.

3.6.2 Reactive Termination Applications

Many countries use a single-pole complex impedance

to model the telephone network transmission line

characteristic impedance as shown in the table below.

Proper gain and termination impedance circuits for a

complex impedance requires the use of complex

network on ZNT as shown in the “Reactive Termination

Application Circuit” on page 8.

3.6.3 Mode Pin Usage

Asserting the MODE pin low (MODE = 0) introduces a

7 dB pad into the transmit path and adds 7 dB of gain

to the receive path. These changes compensate for

the gain changes made to the transmit and receive

paths necessary for reactive termination

implementations. Overall insertion loss with the

reactive termination application circuit and MODE

asserted is 0 dB.

Overall insertion loss with MODE de-asserted

(MODE = 1) for the resistive termination application

circuit is 0 dB.

LITELINK

LITELINK

TXA1

TXA2

-

+

0.1μf

0.1μf

Low-Voltage Side CODEC or

Transmit Circuit

Low-Voltage Side CODEC or

Transmit Circuit

TX-

TX+

TXA1

-

+

TX-

TX+

N/C

1V

------------- 0.008A

+

=

Line Impedance Model

Australia

China

TBR 21

220



200



270



820



680



750



120 nF

100 nF

150 nF

R

S

R

P

C

P