LM25085AMYSLASHNOPB datasheet(13/31 Pages) TI1

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LM25085A

PGATE

ISEN

VCC

ADJ

CADJ

RADJ

LM25085A

CURRENT LIMIT

COMPARATOR

GATE

DRIVER

40 PA

ADJ

RADJ

CADJ

40 PA

GATE

DRIVER

CURRENT LIMIT

COMPARATOR

ISEN

PGATE

VCC

RSEN

USING Q1 RDS(ON)

USING SENSE RESISTOR RSEN

VIN

VIN x tON

tOFF

VFD + VESR t

LM25085A

www.ti.com

SNVS601B – JANUARY 2009 – REVISED MARCH 2013

The on-time in Equation 9 is shorter than the normal on-time since the PFET is shut off when the current limit

threshold is crossed. If the off-time is not long enough, such that the current decrease (Equation 10) is less than

the current increase (Equation 9), the current levels are higher at the start of the next on-time. This results in a

further decrease in on-time, since the current limit threshold is crossed sooner. A balance is reached when the

current changes in Equation 9 and Equation 10 are equal. The worst case situation is that of a direct short circuit

at the output terminals, where VOUT = 0 volts, as that results in the largest current increase during the on-time,

and the smallest decrease during the off-time. The sum of the diode’s forward voltage and the inductor’s ESR

voltage must be sufficient to ensure current runaway does not occur. Using Equation 9 and Equation 10, this

requirement can be stated as:

(11)

For tON in Equation 11 use the minimum on-time at the SW node. To determine this time period add the

“Minimum on-time in current limit” specified in Electrical Characteristics (tON-4) to the difference of the turn-off

and turn-on delays of the PFET. For tOFF use the value in Figure 10, or use Equation 8, where VFB is equal to

zero volts. When using the minimum or maximum limits of those specifications to determine worst case

situations, the tolerance of the minimum on-time (tON-4) and the current limit off-times (tOFF(CL1) through tOFF(CL4))

track each other over the process and temperature variations. A device which has an on-time at the high end of

the range will have an off-time that is at the high end of its range.

Figure 26. Current Limit Sensing

VCC REGULATOR

The VCC regulator provides a regulated voltage between the VIN and the VCC pins to provide the bias and gate

current for the PFET gate driver. The 0.47 µF capacitor at the VCC pin must be a low ESR capacitor, preferably

ceramic as it provides the high surge current for the PFET’s gate at each turn-on. The capacitor must be located

as close as possible to the VIN and VCC pins to minimize inductance in the PC board traces.

Referring to the Figure 7, the voltage across the VCC regulator (VIN – VCC) is equal to VIN until VIN reaches

approximately 8.5V. At higher values of VIN, the voltage at the VCC pin is regulated at approximately 7.7V below

VIN. The VCC regulator has a maximum current capability of at least 20 mA. The regulator is disabled when the

LM25085A is shutdown using the RT pin, or when the thermal shutdown is activated.

PGATE DRIVER OUTPUT

The PGATE pin output swings between VIN (Q1 off) and the VCC pin voltage (Q1 on). The rise and fall times

depend on the PFET gate capacitance and the source and sink currents provided by the internal gate driver. See

Electrical Characteristics for the current capability of the driver.

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