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UPD720100AGM-8ED 数据表(PDF) 8 Page - NEC

部件名 UPD720100AGM-8ED
功能描述  MOS INTEGRATED CIRCUIT
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NEC [NEC]
网页  http://www.nec.com/
标志 NEC - NEC

UPD720100AGM-8ED 数据表(HTML) 8 Page - NEC

Back Button UPD720100AGM-8ED Datasheet HTML 4Page - NEC UPD720100AGM-8ED Datasheet HTML 5Page - NEC UPD720100AGM-8ED Datasheet HTML 6Page - NEC UPD720100AGM-8ED Datasheet HTML 7Page - NEC UPD720100AGM-8ED Datasheet HTML 8Page - NEC UPD720100AGM-8ED Datasheet HTML 9Page - NEC UPD720100AGM-8ED Datasheet HTML 10Page - NEC UPD720100AGM-8ED Datasheet HTML 11Page - NEC UPD720100AGM-8ED Datasheet HTML 12Page - NEC Next Button
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Data Sheet S15535EJ2V0DS
8
µµµµPD720100A
1.
PIN INFORMATION
(1/2)
Pin Name
I/O
Buffer Type
Active
Level
Function
AD (31 : 0)
I/O
5 V PCI I/O
PCI “AD [31 : 0]” signal
CBE (3 : 0)0
I/O
5 V PCI I/O
PCI “C/BE [3 : 0]” signal
PAR
I/O
5 V PCI I/O
PCI “PAR” signal
FRAME0
I/O
5 V PCI I/O
PCI “FRAME#” signal
IRDY0
I/O
5 V PCI I/O
PCI “IRDY#” signal
TRDY0
I/O
5 V PCI I/O
PCI “TRDY#” signal
STOP0
I/O
5 V PCI I/O
PCI “STOP#” signal
IDSEL
I
5 V PCI Input
PCI “IDSEL” signal
DEVSEL0
I/O
5 V PCI I/O
PCI “DEVSEL#” signal
REQ0
O
5 V PCI Output
PCI “REQ#” signal
GNT0
I
5 V PCI Input
PCI “GNT#” signal
PERR0
I/O
5 V PCI I/O
PCI “PERR#” signal
SERR0
O
5 V PCI N-ch Open Drain
PCI “SERR#” signal
INTA0
O
5 V PCI N-ch Open Drain
Low
PCI “INTA#” signal
INTB0
O
5 V PCI N-ch Open Drain
Low
PCI “INTB#” signal
INTC0
O
5 V PCI N-ch Open Drain
Low
PCI “INTC#” signal
PCLK
I
5 V PCI Input
PCI “CLK” signal
VBBRST0
I
5 V PCI Input
Low
Hardware Reset for Chip
CRUN0
I/O
5 V PCI I/O
PCI “CLKRUN#” signal
PME0
O
5 V PCI N-ch Open Drain
Low
PCI “PME#” signal
VCCRST0
I
5 V tolerant Input
Low
RESET for Power Management
SMI0
O
5 V tolerant N-ch Open Drain
Low
System management interrupt output
PIN_EN
I
5 V tolerant Input
High
PCI Interface enable
XT1/SCLK
I
Input
System clock input or Oscillator In
XT2
O
Output
Oscillator Out
DP (5 : 1)
I/O
USB high speed D+I/O
USB’s high speed D+ signal
DM (5 : 1)
I/O
USB high speed D
−I/O
USB’s high speed D
− signal
RSDP (5 : 1)
O
USB full speed D+ O
USB’s full speed D+ signal
RSDM (5 : 1)
O
USB full speed D
− OUSB’s full speed D− signal
OCI (5 : 1)
I (I/O)
5 V tolerant Input
Low
USB Root Hub Port’s overcurrent status input
PPON (5 : 1)
O (I/O)
5 V tolerant Output
High
USB Root Hub Port’s power supply control output
LEGC
I (I/O)
Input
High
Legacy support switch
IRI1
I (I/O)
5 V tolerant Input
High
INT input from keyboard
IRI2
I (I/O)
5 V tolerant Input
High
INT input from mouse
IRO1
O
5 V tolerant Output
High
INT output from keyboard
IRO2
O
5 V tolerant Output
High
INT output from mouse
A20S
O
5 V tolerant 3-state Output
GateA20 State output



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