DP8464B datasheet(13/26 Pages) NSC

13 / 26 page

Application Information (Continued)

Finally the previous AGC level is held This AGC hold func-

tion is accomplished by not allowing any current to charge

up the external CAGC The voltage across this capacitor will

slowly reduce due to the bias current into the Darlington

(see

Figure 6 ) or through any resistor placed in parallel with

CAGC Therefore as described in the Automatic Gain Con-

trol section the gain of the amplifier will slowly increase All

of these three events happen simultaneously

When the READ WRITE input is returned low the pulse

detector will go back to the read mode in a specific se-

quence First of all the input impedance at the Amp In is

returned to 1k Then after approximately 1 ms the Gain

Controlled Amplifier is taken out of the squelch mode and

finally approximately 1 ms after that the AGC circuit is

turned back on This return to the read mode is designed to

minimize analog transients in order to provide stable opera-

tion after 25 ms It is very important that the analog input be

stable before the chip is returned to the read mode It is

recommended that other than when writing the Pulse De-

tector be in the read mode at all times in order to prevent

the 25 ms delay from slowing up the system The READ

WRITE pin may be connected to the Write Gate output of a

controller (such as the DP8466 Disk Data Controller)

TIME CHANNEL FILTER

The peak detection is performed by feeding the output of

the Gain Controlled Amplifier through an external filter to

the differentiator The differentiator output changes state

when the input pulse changes direction generally this will

be at the peaks The differentiator can also respond to

noise near the baseline in which case the comparator gat-

ing channel will inhibit the output The purpose of the exter-

nal filter is to bandwidth limit the incoming signal for noise

considerations Care must be used in the design of this filter

to ensure the delay is not a function of frequency For this

reason a high order Bessel filter with its constant group

delay characteristics can be used in this application Often

this filter must be specifically designed to correct errors in-

troduced by the non-ideal phase characteristics of the input

read head The typcial b3 dB point for this filter is around

15 times the highest recorded frequency The design of this

filter is complex and will not be discussed here However

the following discussion does give a feel for some of the

considerations involved in the filter design The reader is

referred to reference

3 listed at the end of the Applica-

tions Notes for further filter design information

Figure 10 shows a typical Region 1 waveform where there is

no bit interaction This waveform is primarily the sum of the

fundamental frequency and its 3rd harmonic (higher odd

harmonics are present when there is more shouldering)

If the filter is to preserve this wave shape (this would be the

case if no readwrite head phase compensation were nec-

essary) then the phase relationship between the fundamen-

tal frequency and its harmonics must not be altered

Figure

11 shows the output when the 3rd harmonic has the proper

magnitude but the phase relationship is not maintained

The result is that the output waveform is not the same

shape as the input (in a severe case it may be almost unrec-

ognizable) and the time position of the peaks has been al-

tered

One electrical parameter which describes how well a filter

will preserve a wave shape is called group delay Group

delay is defined as the change in phase divided by the

change in frequency If the group delay is constant over the

TLF5283 – 15

FIGURE 10 Typical Region 1 Waveform

TLF5283 – 16

FIGURE 11 Region 1 Waveform with

the Incorrect Phase Relationship

frequencies of interest then the wave shape will be main-

tained An MFM coded signal will contain three basic fre-

quency components for the various digital patterns of data

For instance a 10 Megabitsec MFM signal will consist of

analog frequencies of 25 MHz 333 MHz and 5 MHz On

the outer track the bit density is the lowest and the 5 and

333 MHz signals will look sinusoidal while the 25 MHz sig-

nal will have a tendency to return to the baseline This re-

turning to the baseline is called shouldering and is illustrated

Figure 10 Since this shouldering is rich in 3rd harmonic

the 25 MHz signal will have a strong 75 MHz component

The 10 Megabitsec MFM signal will therefore have

25 MHz 333 MHz 5 MHz and 75 MHz components which

must be filtered with constant group delay in order to repro-

duce the original waveform For example if the phase shift

through the filter at 25 MHz is 333 then at 333 MHz the

phase shift must be 443

at 5 MHz666

and at

75 MHz999

The group delay

for this case is

1332 MHz This can be better interpreted as a time delay

333 of a 25 MHz signal is equivalent to (333360) c

(125 MHz) or 37 ns Similarly 666 on a 5 MHz signal is

(666360) c (15 MHz) e 37 ns

The third order Bessel Filter as shown in the 10 Mbitsec

pulse pairing measurement board on the data sheet is de-

signed for a constant group delay and a b3 dB point of

75 MHz At this frequency the delay through the filter is 35

ns The Gain Controlled Amplifier of the DP8464B is de-

signed for a group delay of a 78 ns g05 ns for frequencies

up to 75 MHz The 78 ns delay in the Gain Controlled

Amplifier and the 37 ns delay in the Bessel Filter do not

introduce any timing error only a delay of 443 ns from the

Amp Input to the output of the filter

DIFFERENTIATOR

A simplified circuit of the first stage of the differentiator is

shown in

Figure 12 The voltages at V3 and V4 are simply

two diodes down from V1 and V2 Therefore the voltage

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