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PCM1702P 数据表(PDF) 2 Page - Texas Instruments |
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PCM1702P 数据表(HTML) 2 Page - Texas Instruments |
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2 / 11 page ![]() 2 ® PCM1702 SPECIFICATIONS All specifications at 25 °C, ±V CC and +VDD = ±5V unless otherwise noted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PCM1702P/U, -J, -K PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 20 Bits DYNAMIC RANGE, THD + N at –60dB Referred to Full Scale, with A-weight 110 dB DIGITAL INPUT Logic Family TTL/CMOS Compatible Logic Level: V IH +2.4 +V DD V V IL 0 0.8 V I IH V IH = +VDD ±10 µA I IL V IL = 0V ±10 µA Data Format Serial, MSB First, BTC(1) Input Clock Frequency 12.5 20.0 MHz TOTAL HARMONIC DISTORTION + N(2) P/U V O = 0dB f S = 352.8kHz (3), f = 1002Hz(4) –92 –88 dB V O = –20dB f S = 352.8kHz (3), f = 1002Hz(4) –82 –74 dB V O = –60dB f S = 352.8kHz (3), f = 1002Hz(4) –46 –40 dB P/U, -J V O = 0dB f S = 352.8kHz (3), f = 1002Hz(4) –96 –92 dB V O = –20dB f S = 352.8kHz (3), f = 1002Hz(4) –83 –76 dB V O = –60dB f S = 352.8kHz (3), f = 1002Hz(4) –48 –42 dB P/U, -K V O = 0dB f S = 352.8kHz (3), f = 1002Hz(4) –100 –96 dB V O = –20dB f S = 352.8kHz (3), f = 1002Hz(4) –84 –80 dB V O = –60dB f S = 352.8kHz (3), f = 1002Hz(4) –50 –44 dB ACCURACY Level Linearity At –90dB Signal Level ±0.5 dB Gain Error ±0.5 ±3% Bipolar Zero Error(5) ±0.25 % Gain Drift 0 °C to 70°C ±25 ppm of FSR/ °C Bipolar Zero Drift 0 °C to 70°C ±5 ppm of FSR/ °C Warm-up Time 1 minute IDLE CHANNEL SNR(6) Bipolar Zero, A-weighted Filter 110 120 dB ANALOG OUTPUT Output Range ±1.2 mA Output Impedance 1.0 k Ω Settling Time ( ±0.003% of FSR, 1.2mA Step) 200 ns Glitch Energy No Glitch Around Zero POWER SUPPLY REQUIREMENTS Supply Voltage Range: +V CC = +VDD +4.75 +5.00 +5.25 V –V CC = –VDD –4.75 –5.00 –5.25 V Combined Supply Current: +I CC +V CC = +VDD = +5V +5.00 +9.0 mA Combined Supply Current: –I CC –V CC = –VDD = –5V –25.00 –41.0 mA Power Dissipation ±V CC = ±VDD = ±5V 150 250 mW TEMPERATURE RANGE Operating –25 +85 °C Storage –55 +125 °C NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (Distortion RMS + NoiseRMS) / SignalRMS. (3) D/A converter sample frequency (8 x 44.1kHz; 8x oversampling). (4) D/A converter output frequency (signal level). (5) Offset error at bipolar zero. (6) Measured using an OPA627 and 5k Ω feedback and an A-weighted filter. |
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