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6

PCM1728

SYSTEM CLOCK

96kHz is not accepted.

The system clock can be either a crystal oscillator placed

between XTI (pin 5) and XTO (pin 6), or an external clock

input to XTI. If an external system clock is used, XTO is

open (floating). Figure 1 illustrates the typical system clock

connections.

PCM1728 has a system clock detection circuit which auto-

(pin 1) clock. LRCIN (left-right clock) operates at the sam-

nized, PCM1728 can compensate for the phase difference

internally. If the phase difference between left-right and

system clocks is greater than 6-bit clocks (BCKIN), the

synchronization is performed internally. While the synchro-

nization is processing, the analog output is forced to a DC

level at bipolar zero. The synchronization typically occurs in

less than 1 cycle of LRCIN.

SYSTEM CLOCK FREQUENCY - MHz

32kHz

8.1920

12.2880

16.3840

24.5760

44.1kHz

11.2896

16.9340

22.5792

48kHz

12.2880

18.4320

24.5760

96kHz

24.5760

—

NOTE: (1) The internal crystal oscillator frequency cannot be larger than 24.576MHz.

TABLE I. Typical System Clock Frequency.

Typical input system clock frequencies to the PCM1728 are

shown in Table I, also, external input clock timing require-

ments are shown in Figure 2.

FIGURE 1. System Clock Connection.

FIGURE 2. XTI Clock Timing.

System Clock

(256/384/

512/768f

Externl Clock Input

CLKO

XTI

XTO

4

5

6

PCM1728

System Clock

Buffer Out

Crystal Resonator Oscillation

CLKO

XTI

XTO

4

5

6

PCM1728

XTAL

C

1

C

2

C

Buffer

t

SCKH

System Clock Pulse Width High t

System Clock Pulse Width Low t

t

SCKL

2.0V

0.8V

“H”

“L”

XTI

DATA INTERFACE FORMATS

Digital audio data is interfaced to PCM1728 on pins 1, 2,

and 3, LRCIN (left-right clock), DIN (data input) and

and left justified data formats.

Figure 3 illustrates acceptable input data formats. Figure 4

shows required timing specification for digital audio data.

Reset

PCM1728 has both internal power-on reset circuit and the

RST pin (pin 22), which accepts an external forced reset by

RST = LOW. For internal power on reset, initialization is

internal reset = LOW, the output of the DAC is invalid and

the timing of the internal power on reset.

PCM1728 accepts an external forced reset when RST = LOW.

When RST = LOW, the output of the DAC is invalid and the

(1024 system clocks count after RST = HIGH.) Figure 6

illustrates the timing of the RST pin.

Zero Out (pin 21)

If the input data is continuously zero for 65536 cycles of

BCK, an internal FET is switched to “ON”. The drain of the

internal FET is the zero-pin, it will enable “wired-or” with

external circuit.