8

Oct10-07 RevJ

SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator

© 2007 Sipex Corporation

APPLICATIONS INFORMATION

VOUT

C3

10

µF

R

FBH

R

FBL

SYNC

SD

Cc

10nF

Rz

4k

Ω

4.7

µH

L1

R1

10

Ω

C2

1

µF

C1

10

µF

VIN

SP6652

1

2

3

4

5

10

9

8

7

6

PGND

SGND

FB

COMP

SD

LX

PVIN

SVIN

SYNC

MODE

Complete Application Circuit.

The SP6652 PWM buck regulator circuit

for the output are typically recommended.

For the input capacitor, a value even larger

than 10µF will help reduce input voltage

ripple for applications sensitive to ripple on

the battery voltage. See the Typical Per-

formance Characteristics section for wave-

forms on input and output ripple with 10µF

capacitors. All the capacitors should be

surface mount ceramic for low lead induc-

tance necessary at the 1.4MHz switching

frequency of the SP6652 and to obtain low

ESR. This also helps improve bypassing

on the input pin and ripple on the output.

Ceramic capacitors with X5R or X7R tem-

perature grade are recommended for most

applications. A selection of recommended

capacitors is included in Table 1. The 1µF

input capacitor should have a series

resistor of about 10Ω value connected

low pass filter to remove high frequency

spikes present on the input switching pin

COMPONENT SELECTION

. This will keep the SP6652 internal

reference and other sensitive circuits noise

free and ensure better output regulation.

the output capacitor should be connected

nect to the thermal pad ground located un-

der the SP6652. The GND return for the

pin, which should be connected

the Typical SP6652 Circuit Layout for de-

tails on the recommended layout.

Output Voltage Selection

To set the output voltage for the SP6652,

voltage divider between the output voltage

at the output capacitor and the FB pin and

GND, as shown in the typical application cir-

sistor is 100KΩ to 200KΩ to keep the quies-

cent current low, but not have the impedance

too high at the FB pin for good regulation.