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LPC2105 数据表(PDF) 18 Page - NXP Semiconductors |
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LPC2105 数据表(HTML) 18 Page - NXP Semiconductors |
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18 / 32 page ![]() Philips Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers Product data Rev. 04 — 05 February 2004 18 of 32 9397 750 12792 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 6.14.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate Watchdog reset. • Programmable 32-bit timer with internal pre-scaler. • Selectable time period from (tpclk × 256 × 4) to (tpclk × 232 × 4) in multiples of tpclk × 4. 6.15 Real time clock The Real Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode). 6.15.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra Low Power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Programmable Reference Clock Divider allows adjustment of the RTC to match various crystal frequencies. 6.16 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2104, LPC2105 and LPC2106. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. It also includes four capture inputs to save the timer value when an input signal transitions, and optionally generate an interrupt when those events occur. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single |
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