SC28L91 datasheet(13/42 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22

Unit

Max

Typ

Min

Parameter

Symbol

Receiver Timing, external clock (See Figure 13)

t*RXS

RxD data setup time to RxC high

t*RXH

RxD data hold time from RxC high

68000 or Motorola bus timing (See Figures 6, 7, 8)10

tDCR

DACKN Low (read cycle) from X1 High10

tDCW

DACKN Low (write cycle) from X1 High

tDAT

DACKN High impedance from CEN or IACKN High

tCSC

CEN or IACKN setup time to X1 High for minimum DACKN cycle

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of

5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8 V and

2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.

3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: CL = 125 pF,

constant current source = 2.6 mA.

4. Typical values are the average values at +25

°C and 5 V.

5. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and

WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.

6. Guaranteed by characterization of sample units.

7. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must

be negated for tRWD to guarantee that any status register changes are valid.

8. Minimum frequencies are not tested but are guaranteed by design.

9. Clocks for 1X mode should maintain a 60/40 duty cycle or better.

10. Minimum DACKN time is tDCR = tDSC + tDCR + two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used

while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be

written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the

bus cycle. DACKN low or CEN high completes the write cycle.

100

120

140

160

180

200

220

240

VCC = 3.3V @ +25°C

5.0V @ +25

°C

Tdd

(ns)

125 pF

30 pF

230 pF

SD00684

12 pF

100 pF

NOTES:

Bus cycle times:

(80XXX mode): tDD + tRWD = 70 ns @ 5V, 40 ns @ 3.3 V + rise and fall time of control signals

(68XXX mode) = tCSC + tDAT + 1 cycle of the X1 clock @ 5 V + rise and fall time of control signals

Figure 3. Port Timing vs. Capacitive Loading at typical conditions

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