SN54F00, SN74F00

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SDFS035A – MARCH 1987 – REVISED OCTOBER 1993

Copyright

2–3

POST OFFICE BOX 655303

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

description

These devices contain four independent 2-input

NAND gates. They perform the Boolean functions

Y = A

• B or Y = A + B in positive logic.

The SN54F00 is characterized for operation over

the full military temperature range of – 55

°C to

125

°C. The SN74F00 is characterized for

operation from 0

°C to 70°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

Y

H

H

L

L

XH

X

L

H

1

1A

2

1B

4

2A

5

2B

9

3A

10

3B

12

4A

13

4B

&

1Y

3

2Y

6

3Y

8

4Y

11

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

logic diagram (positive logic)

1Y

3

1

1A

2

1B

2Y

6

4

2A

5

2B

3Y

8

9

3A

10

3B

4Y

11

12

4A

13

4B

Pin numbers shown are for the D, J, and N packages.

SN54F00 ...J PACKAGE

SN74F00 ...D OR N PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

4B

4A

4Y

3B

3A

3Y

SN54F00 . . . FK PACKAGE

(TOP VIEW)

32

1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

4A

NC

4Y

NC

3B

1Y

NC

2A

NC

2B

NC – No internal connection

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.