TUSB5052 datasheet(18/82 Pages) TI

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3−6

3.3

Setting the TRST and TEST[2:0] Pins for Various Applications

Various combinations of the TRST and TEST[2:0] pins must be grounded to enable the following operational modes.

•

6-MHz operation. This is the normal operational mode. A 6-MHz crystal is required. To enable this mode,

TRST and TEST[2:0] are tied high.

•

48-MHz operation. This mode bypasses the internal APLL. A 48-MHz external oscillator or clock source is

required. To enable this mode, TEST[2:0] must be grounded. TRST must be tied high.

•

Bypassing the internal hub. In this mode, downstream port 1 to port 5 is disabled. Port 6 (function) is logically

connected directly to the upstream port. To enable this mode, TEST1 and TEST0 must be grounded. The

TRST and TEST2 pins must be tied high. A 6-MHz crystal is required in this mode.

For 6-MHz operation, the TUSB5052 requires a 6-MHz crystal to be connected across the XTAL1 and XTAL2 pins.

Internal APLL circuitry generates a 48-MHz internal clock to sample the data from the upstream port. For 48-MHz

operation, the device accepts a 48-MHz clock on the XTAL1 input, and the XTAL2 input should be left unconnected.

A crystal cannot be used in this case. If low-power suspend and resume are desired, a 6-MHz crystal/resonator must

be used, unless there is a way to stop the 48-MHz clock source. If the 48-MHz clock is stopped in suspend mode,

it has to be turned on in the event of a remote wake-up in order for the device to pass the resume signal upstream.

If an oscillator is used by connecting its output to the XTAL1 pin and leaving the XTAL2 pin open, its TTL output level

cannot exceed 3.6 V. Figure 3−4 shows a sample crystal circuit.

XTAL1

XTAL2

NOTE: Figure 3−4 assumes a 6-MHz fundamental crystal that is parallel-loaded. The component values of C1, C2 and Rd were determined

using a crystal from Fox Electronics—part number HC49U−6.00MHz30\50\0

±70\20—which means ±30 ppm at 25°C and 50 ppm from

°C to 70°C. The characteristics for the crystal are load capacitance (CL) of 20 pF, maximum shunt capacitance (Co) of 7 pF and a

maximum ESR of 50

Ω. If the load capacitance is lower, then the maximum ESR can be higher. For example, if CL = 15 pF and Co =

7 pF, then a maximum ESR of 100

Ω will still work. In order to ensure enough negative resistance, use C1 = C2 = 2

CL − 5 pF stray

capacitance. The resistor Rd is used to trim the gain, and Rd = 2.2 kΩ is recommended.

Figure 3−4. Crystal Circuit

3.4

Pin State in Suspend Mode

In suspend mode, the following pins become high-impedance:

DP/DM—USB data bus

When going into suspend mode, the following pins remain in their pre-suspended state:

P1—8051 GPIO

P3—8051 GPIO

LED-1 to LED-4—Hub downstream port status

GPIO[7:0], GPO1, GPO2, and GPO3—general-purpose inputs and outputs

DTR, RTS, SOUT—UART outputs

SDA, SCL—I2C

CLKO—Clock output

RSTO—Reset output

PUR—Pullup resistor connection

PWRO—Power on/off control signal

All the input pins must be pulled to either high or low to prevent the bus line from oscillating.

The output of the SUSP pin relative to other conditions of the device is listed in Table 3−5.

TUSB5052 数据表(PDF) 18 Page - Texas Instruments

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