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2016-01-0028

PT0557-1

02/15/16

7

PI4IOE5V9536

4-bit I

low power I/O port

c. Power-on reset

When power is applied to VCC, an internal power-on reset holds the PI4IOE5V9536 in a reset condition until VCC has

initialize to their default states. Thereafter, VCC must be lowered below 0.2 V to reset the device. For a power reset cycle, VCC

must be lowered below 0.2 V and then restored to the operating voltage.

d. I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be

raised above VCC to a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output Port register. Care should

be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance path that exists

between the pin and either VCC or GND.

Figure 4: Simplified schematic of I/Os

After power-on reset, all registers return to default values.