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PCF8575CPWR 数据表(PDF) 20 Page - Texas Instruments |
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PCF8575CPWR 数据表(HTML) 20 Page - Texas Instruments |
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20 / 38 page ![]() VCC Ramp-Up Time to Re-Ramp Time Ramp-Down VIN drops below POR levels VCC_RT VCC_FT VCC_TRR_VPOR50 VCC Ramp-Up Re-Ramp-Up Time to Re-Ramp Time Ramp-Down VCC_RT VCC_RT VCC_FT VCC_TRR_GND PCF8575C SCPS123F – MARCH 2005 – REVISED JANUARY 2015 www.ti.com 10 Power Supply Recommendations 10.1 Power-On Reset Requirements In the event of a glitch or data corruption, PCF8575C can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 20 and Figure 21. Figure 20. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC Figure 21. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 1 specifies the performance of the power-on reset feature for PCF8575C for both types of power-on reset. Table 1. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES(1) PARAMETER MIN TYP MAX UNIT VCC_FT Fall rate See Figure 20 1 100 ms VCC_RT Rise rate See Figure 20 0.01 100 ms VCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 20 0.001 ms VCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 21 0.001 ms Level that VCCP can glitch down to, but not cause a functional VCC_GH See Figure 22 1.2 V disruption when VCCX_GW = 1 μs Glitch width that will not cause a functional disruption when VCC_GW See Figure 22 μs VCCX_GH = 0.5 × VCCx VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V VPORR Voltage trip point of POR on fising VCC 1.033 1.428 V (1) TA = –40°C to 85°C (unless otherwise noted) 20 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: PCF8575C |
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