Figure 1. Operational Amplifier Protection

Figure 2. Sample and Hold Circuit

Typical Sample and Hold circuit with clipping. DPAD diodes reduce offset

voltages fed capacitively from the JFET switch gate.

FIGURE 1

FIGURE 2

2N4117A

R

2N4393

-V

+V

V

OUT

D2

D1

C

DPAD1

CONTROL

SIGNAL

e

in

+V

-15V

+15V

OP-27

D1

D2

D3

D4

+

-

DPAD10

1

SOIC

2

3

45

6

7

8

DIMENSIONS IN

INCHES

0.2284

0.2440

0.189

0.196

0.0075

0.0098

0.021

0.014

0.018

0.050

0.0040

0.0098

0.150

0.157

TO-78

0.335

0.370

0.305

0.335

0.016

0.019

0.165

0.185

0.040

MAX.

DIM. A

0.016

0.021

DIM. B

MIN. 0.500

0.200

0.100

0.100

0.028

0.034

45°

1

3 4

5

7

0.029

0.045

SEATING

PLANE

TO-72

Four Lead

0.230

0.209

DIA.

DIA.

0.195

0.175

0.030

MAX.

0.500 MIN.

0.150

0.115

0.019

0.016

DIA.

4 LEADS

2

1

3

0.046

0.036

45°

0.048

0.028

0.100

0.050

4

1.

Absolute maximum ratings are limiting values above which serviceability may be impaired.

2.

shown are available upon request.

Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its

use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implicatio

otherwise under any patent or patent rights of Linear Integrated Systems.

n or