80%

20%

80%

20%

ODCK

80%

80%

20%

20%

QE[23:0], QO[23:0], DE,

CTL[2:1], HSYNC, VSYNC

ODCK

ODCK

QE[23:0], QO[23:0], DE,

CTL[2:1], HSYNC, VSYNC

OCK_INV

50%

Tx+

Tx-

50%

ODCK

QE[23:0]

PD

QE[23:0], QO[23:0],

ODCK, DE, CTL[2:1],

HSYNC, VSYNC, SCDT

PDO

QE[23:0], QO[23:0],

ODCK, DE, CTL[2:1],

HSYNC, VSYNC

TFP501

www.ti.com

SLDS127C

– JULY 2001 – REVISED JULY 2011

PARAMETER MEASUREMENT INFORMATION

Figure 1. Rise and Fall Time of ODCK

Figure 2. Rise and Fall Time of Data and Control Signals

Figure 3. ODCK Frequency

Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK

Figure 5. ODCK High to QE[23:0]

Figure 6. Analog Input Intra-Pair

Staggered Data Output

Differential Skew

Figure 7. Delay from PD Low to Hi-Z Outputs

Figure 8. Delay from PDO Low to Hi-Z Outputs

Copyright

© 2001–2011, Texas Instruments Incorporated

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