TL16PC564BLVI

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS627− SEPTEMBER 2004

9

POST OFFICE BOX 655303

SSAB

SELZ /I

RD(DS)WR(R/W)

Address

Operation

0

0

0

1

SA8, SAD(7− 0)

Intel read

0

0

1

0

SA8, SAD(7− 0)

Intel write

0

1

0

1

SA8, SAD(7− 0)

Zilog read

0

1

0

0

SA8, SAD(7− 0)

Zilog write

1

0

0

1

SA(8 −0)

Intel read

1

0

1

0

SA(8 −0)

Intel write

1

1

0

1

SA(8 −0)

Zilog read

1

1

0

0

SA(8 −0)

Zilog write

attribute-memory arbitration

Arbitration for the attribute memory is necessary whenever there is simultaneous access to the same DPRAM

or CCR address for the conditions of:

If arbitration were not provided, attribute-memory data would be corrupted and invalid data read due to

uncontrolled access to the same DPRAM or CCR address.

The arbitration control circuitry synchronizes the asynchronous accesses of the host CPU and subsystem to

the DPRAM and CCR and controls the access based on the pending host CPU and subsystem

attribute-memory operation. The synchronizing and control circuitry needs a clock called the arbitration clock.

The external clock (ARBCLKI) goes through a programmable divider and can be divided by one, two, four, or

eight to generate a clock frequency within an allowed range for the arbitration logic to work correctly. The output

of this frequency divider is named ARBCLKO. The programmable divider bits are defined as follows:

ARBPGM1

ARBPGM0

INTERNAL

ARITRATION CLOCK

L

L

ARBCLKI/1

L

H

ARBCLKI/2

H

L

ARBCLKI/4

H

H

ARBCLKI/8

The upper period limit of ARBCLKO is N/6, where N (ns) is the shortest of the two attribute-memory accesses,

host CPU or subsystem. The lower period limit of ARBCLKO is based on the DPRAM specifications at the supply

voltage used:

5 V = 14-ns clock cycle (71 MHz)

3 V = 26-ns clock cycle (38.5 MHz)

For any arbitration condition, attribute-memory access is controlled to ensure valid data is read for a port that

is doing a read operation and valid data is written for a port that is doing a write operation. When both the host

CPU and subsystem are performing simultaneous write operations to the same address, the host CPU is

allowed to write and the subsystem write is ignored.

host CPU/subsystem handshake

Two signals are provided for handshaking between the host CPU and the subsystem. The active-high IRQ

signifies to the subsystem that the host CPU has written data into attribute memory. The subsystem can clear

IRQ by writing a 1 to bit 6 of the subsystem control register. The active-low STSCHG signifies to the host CPU

Not Recommended For New Designs