LP2989

www.ti.com

SNVS083O – FEBRUARY 2005 – REVISED MARCH 2015

5 Pin Configuration and Functions

D/DGK Packages

NGN Package

8-Pin SOIC and VSSOP

8-Lead WSON

Top View

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

BYPASS

1

I

Bypass capacitor input

ERROR

7

O

Error signal output

GROUND

3

—

GND

INPUT

4

I

Regulator power input

DO NOT CONNECT. Device pin 2 is reserved for post packaging test and calibration of the

Do not connect to ground. Any attempt to do pin continuity testing on device pin 2 is

N/C

2

—

discouraged. Continuity test results will be variable depending on the actions of the factory

calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 2

OUTPUT

5

O

Regulated output voltage

SENSE

6

I

Feedback voltage sense input

SHUTDOWN

8

I

Shutdown input

The exposed thermal pad on the bottom of the WSON package should be connected to a

copper thermal pad on the PCB under the package. The use of thermal vias to remove heat

from the package into the PCB is recommended. Connect the thermal pad to ground

Thermal Pad

—

—

potential or leave floating. Do not connect the thermal pad to any potential other than the

same ground potential seen at device pin 3. For additional information on using TI's Non Pull

Back WSON package, see Application Note AN-1187 Leadless Leadframe Package (LLP)

(SNOA401).

Copyright © 2005–2015, Texas Instruments Incorporated

Submit Documentation Feedback

3

Product Folder Links: LP2989