LP3907TLX-JSXSSLASHNOPB datasheet(47/58 Pages) TI1

47 / 58 page

LP3907

www.ti.com

SNVS511S – JUNE 2007 – REVISED APRIL 2016

Product Folder Links: LP3907

Submit Documentation Feedback

11 Layout

11.1 DSBGA Layout Guidelines

PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance

of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss

in the traces. These can send erroneous signals to the DC-DC converter device, resulting in poor regulation or

instability.

Good layout for the LP3907 device bucks can be implemented by following a few simple design rules below.

Refer to Figure 49 for top-layer board buck layout.

1. Place the LP3907 bucks, inductor, and filter capacitors close together and make the traces short. The traces

between these components carry relatively high switching currents and act as antennas. Following this rule

reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN

and GND pin.

2. Arrange the components so that the switching current loops curl in the same direction. During the first half of

each cycle, current flows from the input filter capacitor through the LP3907 bucks and inductor to the output

filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is

pulled up from ground through the LP3907 bucks by the inductor to the output filter capacitor and then back

through ground forming a second current loop. Routing these loops so the current curls in the same direction

prevents magnetic field reversal between the two half-cycles and reduces radiated noise.

3. Connect the ground pins of the LP3907 bucks and filter capacitors together using generous component-side

copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several

vias. This reduces ground-plane noise by preventing the switching currents from circulating through the

ground plane. It also reduces ground bounce at the LP3907 bucks by giving it a low-impedance ground

connection.

4. Use wide traces between the power components and for power connections to the DC-DC converter circuit.

This reduces voltage errors caused by resistive losses across the traces.

5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power

components. The voltage feedback trace must remain close to the circuit of the LP3907 buck and must be

direct but must be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC

converter’s own voltage feedback trace. A good approach is to route the feedback trace on another layer and

to have a ground plane between the top layer and layer on which the feedback trace is routed. In the same

manner for the adjustable part it is desired to have the feedback dividers on the bottom layer.

6. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks

and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced through

distance.

For more detailed layout specifications and information, refer to AN-1112 DSBGA Wafer Level Chip Scale

Package (SNVA009).

LP3907TLX-JSXS/NOPB 数据表(PDF) 47 Page - Texas Instruments

LP3907TLX-JSXS/NOPB 数据表(HTML) 47 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表下载