CS5516 datasheet(21/41 Pages) CIRRUS

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SID pin is not being written. When reading

SOD, SCLK cannot be continuous but must

burst one clock cycle per bit.

The continuous read conversion data mode is

also functional in the 3-wire interface mode. Is-

sue one 88(H) command word to the converter.

Then wait for SOD to go low. Issue 8 SCLKs to

clear the data ready function. The MSB data bit

will then appear on the SOD pin. Issue 24

SCLKs to read the conversion word. At the fall-

ing edge of the 24th SCLK SOD will return

high. SOD will go low at the next DRDY falling

time to indicate a new conversion word. Eight

SCLKs must again be issued to clear the data

ready function before clocking out the data con-

version word. The SOD pin will continue to

toggle low each time a word is available even if

the conversion data is not read. To terminate the

continuous conversion mode, input an 8-bit com-

man d word immediat el y after read ing a

conversion word.

The user should perform all data reads and com-

mand writes within 51,000 XIN clock cycles

after SOD falls to avoid ambiguity as to who

controls the serial port.

Serial Port Initialization

If for any reason the off-chip microcontroller

fails to know whether the serial port of the

CS5516/20 is in data mode or command mode,

the following initialization procedure can be is-

sued to the port to force the CS5516/20 into the

command mode. Write 128 or more 1’s to the

SID pin. Then issue a single 0 to the SID pin.

The port will then be initialized into the com-

mand mode and will be waiting for an 8-bit

command word.

Bridge Excitation Options

The CS5516/CS5520 A/D converters are opti-

mized for Wheatstone bridge applications. The

converters support either dc or ac (switched dc)

bridge excitation.

DC Bridge Excitation

The CS5516/CS5520 can be configured for dc

bridge excitation in either of two ways.

The

EXC bit of the configuration register can be set

for either internal or for external excitation. If

set to internally-controlled mode (EXC = 0), the

F1 and F0 bits must be set to logic 0s. In this

condition, the bridge can be excited from a dc

supply with a resistor divider to develop the ap-

propriate reference voltage for the VREF+ and

VREF- pins. Note that the bridge excitation

8 Data Bits

24 Data Bits

SCLK

SID

DRDY

SOD

24 Data Bits

8 SCLKs

24 SCLKs

Port Access Period

Valid 51,000

XIN Clock Cycles

81,920 XIN

Clock Cycles

Figure 5. Continuous Read Conversion Data Mode (4 or 5 Wire)

CS5516, CS5520

DS74F1

DS74F2

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