TLC320AD50CSLASHI datasheet(21/57 Pages) TI1

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2–6

2.2

Reset and Power-Down Functions

2.2.1

Software and Hardware Reset

The TLC320AD50C and TLC320AD52C reset the internal counters and registers in response to either of two events:

A low-going reset pulse is applied to terminal RESET.

A 1 is written to the programmable software reset bit (D7 of control register 1).

Either event resets the control registers and clears all the sequential circuits in the device. Reset signals should be

at least 6 master clock periods long.

After hardware reset, the default contents of all registers is 0.

After a hardware or software reset, the AD50 and AD52 require a finite amount of time for the internal PLL to stabilize.

During this time, no control words or D/A data should be written to the device.

The reset sequence should be as follows:

Assert reset (pulse width encompassing at least 6 MCLK periods)

Deactivate reset

Wait for SCLKS to be generated by the master device. This will take approximately 100

µs.

Wait for 18 frame syncs to occur

Write control and configuration data

Collect conversion data

2.2.2

Software and Hardware Power Down

Except for the digital interface, most of the device enters the power-down mode when D6 in control 1 register is set

to 1. When PWRDWN is taken low, the entire device is powered down. In either case, the register contents are

preserved and the output of the monitor amplifier is held at the midpoint voltage to minimize pops and clicks.

The amount of power drawn during software power down is higher than it is during a hardware power down because

of the current required to keep the digital interface active. Additional differences between software and hardware

power-down modes are detailed in the following paragraphs. Figure 2–7 represents the internal power-down logic.

PWRDWN

D6 is Programmed

Through a Secondary

Write Operation

Software Power Down

(Control Register 1, D6)

Internal TLC320AD50C

Figure 2–7. Internal Power-Down Logic

2.2.2.1 Software Power Down

When D6 of control 1 register is set to 1, the device enters the software power-down mode. In this state, the digital

interface circuit is still active while the internal ADC and DAC channels and differential outputs OUTP and OUTM are

disabled, and DOUT and FSD are inactive. Register data in the secondary serial communications is still accepted,

but data in the primary serial communications is ignored. The device returns to normal operation when D6 of control

1 register is reset to 0.

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