TLC352

LinCMOS DUAL DIFFERENTIAL COMPARATOR

SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002

6

POST OFFICE BOX 655303

PARAMETER INFORMATION

Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the

comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a

triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual

dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input

is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop

reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which

can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input

exactly equals the input offset voltage.

Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement

easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is

suggested that their tolerance level be 1% or lower.

Measuring the extremely low values of input current requires isolation from all other sources of leakage current and

compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage

can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from

the measurement obtained with a device in the socket to obtain the actual input current of the device.

+

−

+

−

+

−

DUT

VDD

R5

1.8 k

Ω, 1%

C3 0.68

µF

U1c

1/4 TLC274CN

R7

1M

Ω

R8

1.8 k

Ω, 1%

R9

10 k

Ω, 1%

R2

10 k

Ω

R1

240 k

Ω

Triangle

Generator

Integrator

U1b

1/4 TLC274CN

Buffer

C2

1

µF

R10

100

Ω, 1%

R3

100 k

Ω

VIO

(X100)

C4

0.1

µF

R6

5.1 k

Ω

U1a

1/4 TLC274CN

R4

47 k

Ω

C1

0.1

µF

Figure 2. Circuit for Input Offset Voltage Measurement