INA321

INA2321

SBOS168B − DECEMBER 2000 − REVISED JULY 2004

www.ti.com

13

INPUT PROTECTION

Device inputs are protected by ESD diodes that will

conduct if the input voltages exceed the power supplies by

more than 500mV. Momentary voltages greater than

500mV beyond the power supply can be tolerated if the

current through the input pins is limited to 10mA. This is

Figure 7. Many input signals are inherently current-limited

to less than 10mA; therefore, a limiting resistor is not

required.

R

LIM

R

LIM

I

OVERLOAD

10mA max

INA321

5

3

2

V

OUT

8

7

6

4

1

V+

Shutdown

RG

V

V

−

V

REF

Figure 7. Input Protection

OFFSET VOLTAGE ERROR CALCULATION

maximum of 500

µV with a +5V power supply and the

for power-supply rejection and common-mode rejection

are provided to allow the user to easily calculate

worst-case expected offset under the conditions of a given

application.

Power-Supply Rejection Ratio (PSRR) is specified in

µV/V. For the INA321, worst-case PSRR is 200µV/V,

which means for each volt of change in power supply, the

offset may shift up to 200

µV. Common-Mode Rejection

Ratio (CMRR) is specified in dB, which can be converted

to

µV/V using the following equation:

CMRR (in

For the INA321, the worst-case CMRR over the specified

common-mode range is 90dB (at G = 25) or about 30

µV/V.

This means that for every volt of change in common-mode,

the offset will shift less than 30

µV.

These numbers can be used to calculate excursions from

the specified offset voltage under different application

conditions. For example, an application might configure

the amplifier with a 3.3V supply with 1V common-mode.

This configuration varies from the specified configuration,

representing a 1.7V variation in power supply (5V in the

offset specification versus 3.3V in the application) and a

0.65V variation in common-mode voltage from the

Calculation of the worst-case expected offset would be as

follows:

(power-supply variation)

• PSRR +

(common-mode variation)

• CMRR

=

±0.860mV

However, the typical value will be smaller, as seen in the

Typical Characteristics.

FEEDBACK CAPACITOR IMPROVES RESPONSE

For

optimum

settling

time

and

stability

with

high-impedance feedback networks, it may be necessary

to add a feedback capacitor across the feedback resistor,

the zero created by the feedback network impedance and

the INA321’s RG-pin input capacitance (and any parasitic

layout capacitance). The effect becomes more significant

added to reduce high-frequency noise.

INA321

V+

V

OUT

R

IN

R

R

F

R

X

C

L

C

IN

Where C

(approximately 3pF) plus any parastic layout capacitance.

5

3

2

8

7

6

4

1

Shutdown

RG

V

V

−

V

REF

C

F

Figure 8. Feedback Capacitor Improves Dynamic

Performance

It is suggested that a variable capacitor be used for the

feedback capacitor since input capacitance may vary

between

instrumentation

amplifiers,

and

layout

capacitance is difficult to determine. For the circuit shown

in Figure 8, the value of the variable feedback capacitor

should be chosen by the following equation:

capacitance (typically 3pF) plus the layout capacitance.

The capacitor can be varied until optimum performance is

obtained.