STA400A datasheet(43/117 Pages) STMICROELECTRONICS

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STA400A

PFDTHR - Phase/Frequency Error Detector Threshold

This register sets the threshold for the frequency detector. The number format is positive integer.

SYMFREQ

- Symbol Frequency

This register sets the symbol frequency of the Timing NCO (equal to 1.64MHz for both satellite demodulators).

It is 25 bit long and is divided into four bytes; SYMFREQ0 is the LSB byte, SYMFREQ3 is the MSB. SYMFREQ

must be loaded with an interger value given by

where FMCLK =

23.92MHz is the master clock frequency, Fsym is the symbol frequency and Int(.) is the integer part of the number.

IFFREQ

- Intemediate Frequency

This register sets the 2nd intermediate carrier frequency of the I/Q Mixer. It is 28 bit long and is divided into four

bytes; IFFREQ0 is the LSB byte, IFFREQ3 is the MSB. IFFREQ must be loaded with an interger value given by

where FMCLK = 23.92MHz is the master clock frequency, Fc is the second

intermediate frequency (5.175MHz for S2-Late satellite and 7.015MHz for S1-Early satellite) and Int(.) is the in-

teger part of the number.

Type:

SingleByte - R/W

Word Length:

Byte Name

Address (Hex)

Bit Map

Reset Value (Hex)

PFDTHR

S1/S2

005B/0081

5-0

Type:

MultiBytes - R/W

Word Length:

Byte Name

Address (Hex)

Bit Map

Reset Value (Hex)

SYMFREQ3

S1/S2

005F/0085

SYMFREQ2

S1/S2

005E/0084

23-16

SYMFREQ1

S1/S2

005D/0083

15-8

SYMFREQ0

S1/S2

005C/0082

7-0

Type:

MultiBytes - R/W

Word Length:

Byte Name

Address (Hex)

Bit Map

Reset Value (Hex)

IFFREQ3

S1/S2

0063/0089

27-24

04/03

IFFREQ2

S1/S2

0062/0088

23-16

B1/76

IFFREQ1

S1/S2

0061/0087

15-8

3B/27

IFFREQ0

S1/S2

0060/0086

7-0

14/62

SYMFR EQ

i nt 0.5

sym

MC LK

------------------2







IFF REQ

in t 0.5

MC LK

------------------ 2







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