LPV511 datasheet(12/21 Pages) TI1

12 / 21 page

VIN

RISO

VOUT

LPV511

SNOSAG7C – AUGUST 2005 – REVISED MARCH 2013

www.ti.com

APPLICATION NOTES

The LPV511 is fabricated with Texas Instrument's state-of-the-art VIP50C process.

INPUT STAGE

The LPV511 has a rail-to-rail input which provides more flexibility for the system designer. As can be seen from

the simplified schematic, rail-to-rail input is achieved by using in parallel, one PNP differential pair and one NPN

differential pair. When the common mode input voltage (VCM) is near V

+, the NPN pair is on and the PNP pair is

off. When VCM is near V

−, the NPN pair is off and the PNP pair is on. When V

CM is between V

+ and V−, internal

logic decides how much current each differential pair will get. This special logic ensures stable and low distortion

amplifier operation within the entire common mode voltage range.

Because both input stages have their own offset voltage (VOS) characteristic, the offset voltage of the LPV511

becomes a function of VCM. VOS has a crossover point at 1.0V below V

+. Refer to the ’V

OS vs. VCM’ curve in the

Typical Performance Characteristics section. Caution should be taken in situations where the input signal

amplitude is comparable to the VOS value and/or the design requires high accuracy. In these situations, it is

necessary for the input signal to avoid the crossover point.

The input bias current, IB will change in value and polarity as the input crosses the transition region. In addition,

parameters such as PSRR and CMRR which involve the input offset voltage will also be affected by changes in

VCM across the differential pair transition region.

Differential input voltage is the difference in voltage between the non-inverting (+) input and the inverting input (

−)

of the op amp. Due to the three series diodes across the two inputs, the absolute maximum differential input

voltage is ±2.1V. This may not be a problem to most conventional op amp designs; however, designers should

avoid using the LPV511 as a comparator.

OUTPUT STAGE

The LPV511 output voltage swing 100 mV from rails @ 3V supply, which provides the maximum possible

dynamic range at the output. This is particularly important when operating on low supply voltages.

The LPV511 Maximum Output Voltage Swing defines the maximum swing possible under a particular output

load. The LPV511 output swings 110 mV from the rail @ 5V supply with an output load of 100 k

Ω.

DRIVING CAPACITIVE LOAD

The LPV511 is internally compensated for stable unity gain operation, with a 27 kHz typical gain bandwidth.

However, the unity gain follower is the most sensitive configuration to capacitive load. Direct capacitive loading

reduces the phase margin of the op amp. When the output is required to drive a large capacitive load, greater

than 100 pF, a small series resistor at the output of the amplifier improves the phase margin (see Figure 29).

In Figure 29, the isolation resistor RISO and the load capacitor CL form a pole to increase stability by adding more

phase margin to the overall system. The desired performance depends on the value of RISO. The bigger the RISO

resistor value, the more stable VOUT will be. But the DC accuracy is degraded when the RISO gets bigger. If there

were a load resistor in Figure 29, the output voltage would be divided by RISO and the load resistor.

Figure 29. Resistive Isolation of Capacitive Load

Submit Documentation Feedback

Product Folder Links: LPV511

LPV511 数据表(PDF) 12 Page - Texas Instruments

LPV511 数据表(HTML) 12 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

数据表下载