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TLK2201RCP 数据表(PDF) 13 Page - Texas Instruments |
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TLK2201RCP 数据表(HTML) 13 Page - Texas Instruments |
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13 / 24 page ![]() www.ti.com CL 5 pF CL 5pF 50 Ω 50 Ω LVTTL OUTPUT SWITCHING CHARACTERISTICS tr tf CLOCK 80% 50% 20% tr tf 2 V 0.8 V DATA 1.4 V TRANSMITTER TIMING REQUIREMENTS TLK2201 TLK2201I ETHERNET TRANSCEIVERS SLLS420F – JUNE 2000 – REVISED SEPTEMBER 2007 Figure 8. Transmitter Test Setup over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr(RBC) Clock rise time 0.3 1.5 ns tf(RBC) Clock fall time 0.3 1.5 80% to 20% output voltage, C = 5 pF (see Figure 9) tr Data rise time 0.3 1.5 ns tf Data fall time 0.3 1.5 Data setup time (RD0..RD9), tsu(D1) TBI normal mode (see Figure 3) 2.5 ns Data valid prior to RBC0 rising Data hold time (RD0..RD9), th(D1) TBI normal mode (see Figure 3) 2 ns Data valid after RBC0 rising tsu(D2) Data setup time (RD0..RD4) DDR mode, Rω = 125 MHz (see Figure 4) 2 ns th(D2) Data hold time (RD0..RD4) DDR mode, Rω = 125 MHz (see Figure 4) 0.8 ns tsu(D3) Data setup time (RD0..RD9) TBI half-rate mode, Rω = 125 MHz (see Figure 2) 2.5 ns th(D3) Data hold time (RD0..RD9) TBI half-rate mode, Rω = 125 MHz (see Figure 2) 1.5 ns Figure 9. TTL Data I/O Valid Levels for AC Measurement over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tsu(D4) Data setup time (TD0..TD9) 1.6 TBI modes ns th(D4) Data hold time (TD0..TD9) 0.8 tsu(D5) Data setup time (TD0..TD9) 0.7 DDR modes ns th(D5) Data hold time (TD0..TD9) 0.5 tr, tf TD[0,9] Data rise and fall time See Figure 11 2 ns Copyright © 2000–2007, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s): TLK2201 TLK2201I |
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