2

Pinout

CD54HC74, CD54HCT74

(CERDIP)

CD74HC74, CD74HCT74

(PDIP, SOIC)

TOP VIEW

Functional Diagram

TRUTH TABLE

INPUTS

OUTPUTS

SET

RESET

CP

D

Q

Q

LH

X

X

HL

H

L

XX

L

H

L

L

X

X

H (Note 1)

H (Note 1)

H

H

↑

HH

L

H

H

↑

LL

H

HH

L

X

Q0

Q0

H= High Level (Steady State)

L= Low Level (Steady State)

X= Don’t Care

Q0 = the level of Q before the indicated input conditions were established.

NOTE:

1. This configuration is nonstable, that is, it will not persist when set and reset inputs return to their inactive (high) level.

1R

1D

1CP

1S

1Q

1Q

GND

2R

2D

2CP

2S

2Q

2Q

1

2

3

4

5

6

7

14

13

12

11

10

9

8

RESET

DATA

RESET

SET

1

2

3

13

5

6

Q

Q

10

CLOCK

4

SET

DATA

12

11

9

8

Q

Q

CLOCK

D

CP

R

F/F 2

S

GND = PIN 7

D

CP

R

F/F 1

S

CD54HC74, CD74HC74, CD54HCT74, CD74HCT74