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UCD3138RMHT 数据表(PDF) 15 Page - Texas Instruments

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部件名 UCD3138RMHT
功能描述  Highly Integrated Digital Controller for Isolated Power
PDF  78 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

UCD3138RMHT 数据表(HTML) 15 Page - Texas Instruments

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UCD3138
www.ti.com
SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013
3
Electrical Specifications
3.1
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN
MAX
V33D
V33D to DGND
–0.3
3.8
V
V33DIO
V33DIO to DGND
–0.3
3.8
V
V33A
V33A to AGND
–0.3
3.8
V
BP18
BP18 to DGND
–0.3
2.5
V
|DGND – AGND|
Ground difference
0.3
V
All Pins, excluding
Voltage applied to any pin
–0.3
3.8
V
AGND(2)
TJ
Junction Temperature
–40
150
°C
TSTG
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Referenced to DGND
3.2
THERMAL INFORMATION
UCD3138
UCD3138
UCD3138
THERMAL METRIC(1)
UNITS
64 PIN QFN
40 PIN QFN
40 PIN QFN
(RGC)
(RHA)
(RMH)
θJA
Junction-to-ambient thermal resistance (2)
25.1
31.8
31.0
θJCtop
Junction-to-case (top) thermal resistance (3)
10.5
18.5
16.5
θJB
Junction-to-board thermal resistance (4)
4.6
6.8
6.3
°C/W
ψJT
Junction-to-top characterization parameter(5)
0.2
0.2
0.2
ψJB
Junction-to-board characterization parameter (6)
4.6
6.7
6.3
θJCbot
Junction-to-case (bottom) thermal resistance (7)
1.2
1.8
1.1
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
3.3
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
V33D
Digital power
3.0
3.3
3.6
V
V33DIO
Digital I/O power
3.0
3.3
3.6
V33A
Analog power
3.0
3.3
3.6
V
TJ
Junction temperature
–40
-
125
°C
BP18
1.8V Digital Power
1.6
1.8
2.0
V
Copyright © 2012–2013, Texas Instruments Incorporated
Electrical Specifications
15
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Product Folder Links: UCD3138



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