TNETV2685FIBZUT11 datasheet(149/190 Pages) TI1

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TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

6.17 Peripheral Component Interconnect (PCI)

The device supports connections to a PCI backplane via the integrated PCI master/slave bus interface.

The PCI port interfaces to DSP internal resources via the data switched central resource. .

For more detailed information on the PCI port peripheral module, see the TMS320DM647/DM648

Peripheral Component Interconnect (PCI) User's Guide (literature number SPRUEL4).

6.17.1 PCI Device-Specific Information

The PCI peripheral conforms to the PCI Local Bus Specification (version 2.3). The PCI peripheral can act

both as a PCI bus master and as a target. It supports PCI bus operation of speeds up to 66 MHz and uses

a 32-bit data/address bus.

The pins of the PCI peripheral are multiplexed with the pins of the HPI, and GPIO peripherals. PCI

functionality for these pins is controlled (enabled/disabled) by the UHPIEN pin (H2). The maximum speed

of the PCI, 33 MHz or 66 MHz, is controlled through the PCI66 pin (G5). For more detailed information on

the peripheral control, see Section 3.

The device provides an initialization mechanism through which the default values for some of the PCI

configuration registers can be read from an I2C EEPROM. Table 6-68 shows the registers which can be

initialized through the PCI auto-initialization. Also shown is the default value of these registers when PCI

auto-initialization is not used. PCI auto-initialization is enabled by selecting PCI boot with auto-

initialization. For more information on this feature, see the TMS320DM647/DM648 Peripheral Component

Interconnect (PCI) User's Guide (literature number SPRUEL4) and the Using the TMS320DM647/DM648

Bootloader Application Report (literature number SPRAAJ1).

Table 6-68. Default Values for PCI Configuration

Registers

DEFAULT

VALUE

Vendor ID/Device ID Register (PCIVENDEV)

104C B003h

Class Code/Revision ID Register (PCICLREV)

0000 0001h

Subsystem Vendor ID/Subsystem ID Register

0000 0000h

(PCISUBID)

Max Latency/Min Grant/Interrupt Pin/Interrupt Line

0000 0100h

Peripheral Information and Electrical Specifications

149

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