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TNETV2685FIBZUT11 数据表(PDF) 25 Page - Texas Instruments |
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TNETV2685FIBZUT11 数据表(HTML) 25 Page - Texas Instruments |
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25 / 190 page  TMS320DM647 TMS320DM648 www.ti.com SPRS372H – MAY 2007 – REVISED APRIL 2012 Table 2-4. Terminal Functions (continued) TERMINAL NAME NO TYPE( INTERNAL OPER DESCRIPTION 1) PULLUP/ VOLT PULLDOWN MDIO U8 I/O/Z IPU 3.3 V MDIO Serial Data (MDIO) SPI or UART SPICLK F22 I/O/Z IPU 3.3 V SPI Clock Output SPICS1/UARTTX D23 I/O/Z IPU 3.3 V SPI Chip Select 1 or UART Transmit (O/Z) SPICS2/UARTRX F23 I/O/Z IPU 3.3 V SPI Chip Select 2 or UART Receive SPIDI/UARTRTS G23 I/O/Z IPU 3.3 V SPI Data input or UART Ready to send (O/Z) SPIDO/UARTCTS F21 I/O/Z IPU 3.3 V SPI Data Output or UART Clear to send TIMER 0/1 or GPIO[8:11] T0INP12/GP08 E20 I/O/Z IPD 3.3 V Timer 0 input pin for lower 32-bit counter (I) or GPIO 8 T0OUT12/GP09 D21 I/O/Z IPD 3.3 V Timer 0 output pin for lower 32-bit counter (O/Z) or GPIO 9 T1INPL/GP10 E21 I/O/Z IPD 3.3 V Timer 1 input pin for lower 32-bit counter (I) or GPIO 10 T1OUT12/GP11 C22 I/O/Z IPD 3.3 V Timer 1 output pin for lower 32-bit counter(O/Z) or GPIO 11 McASP OR VIDEO PORT OR VIC AHCLKR AC4 I/O/Z IPD 3.3 V McASP Receive high-frequency master clock AHCLKX AC3 I/O/Z IPD 3.3 V McASP Transmit high-frequency master clock ACLKR AC6 I/O/Z IPD 3.3 V McASP Receive master clock ACLKX AC7 I/O/Z IPD 3.3 V McASP Transmit master clock AFSR W6 I/O/Z IPD 3.3 V McASP Receive Frame sync or left/right clock (LRCLK) AFSX AA7 I/O/Z IPD 3.3 V McASP Transmit Frame sync or left/right clock (LRCLK) AXR0 AB6 I/O/Z IPD 3.3 V McASP Data Pin [0:7] AXR1 Y6 IPD 3.3 V AXR2 AA6 IPD 3.3 V AXR3 AB4 IPD 3.3 V AXR4 Y5 IPD 3.3 V AXR5 V7 IPD 3.3 V AXR6 AA4 IPD 3.3 V AXR7 V6 IPD 3.3 V STCLK/AXR8 Y7 I/O/Z IPD 3.3 V The STCLK signal drives the hardware counter for use by the video ports (I) or McASP data pin 8. VDAC/AXR9 AA5 I/O/Z IPD 3.3 V VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter (VDAC) output (O) or McASP data pin 9 AMUTEIN AB3 I/O/Z IPD 3.3 V McASP Mute Input AMUTE U7 I/O/Z IPD 3.3 V McASP Mute Output VIDEO PORT 0 OR GPIO[12:15] VP0CLK0 Y23 I IPU 3.3 V Video Port 0 Clock 0 (I) VP0CLK1 V23 I/O/Z IPU 3.3 V Video Port 0 Clock 1 VP0CTL0 Y22 I/O/Z IPU 3.3 V Video Port 0 Control 0 VP0CTL1 V22 I/O/Z IPU 3.3 V Video Port 0 Control 1 VP0CTL2 U23 I/O/Z IPU 3.3 V Video Port 0 Control 2 VP0D02 W20 I/O/Z IPD 3.3 V Video Port 0 Data 2 VP0D03 V18 I/O/Z IPD 3.3 V Video Port 0 Data 3 VP0D04 U18 I/O/Z IPD 3.3 V Video Port 0 Data 4 VP0D05 V19 I/O/Z IPD 3.3 V Video Port 0 Data 5 VP0D06 W21 I/O/Z IPD 3.3 V Video Port 0 Data 6 VP0D07 T18 I/O/Z IPD 3.3 V Video Port 0 Data 7 VP0D08 U19 I/O/Z IPD 3.3 V Video Port 0 Data 8 Copyright © 2007–2012, Texas Instruments Incorporated Device Overview 25 Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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