10

®

MPC100

The transient peaks remain less than +2.5mV and –1.2mV.

Subsequent equipment might interpret large negative output

glitches as synchronization pulses. To remove this problem,

the output must be clamped during the switching dead time.

With the MPC100, the generated output transients are ex-

tremely small and clamping is unnecessary. The switching

time between two channels is less than 0.5

µs. This short

time period allows easy switching during the vertical blank-

ing time. The signal envelope during the transition from one

channel to another rises and falls symmetrically and shows

less overshooting or DC settling transients.

Power consumption is a serious problem when designing

large crosspoint fields with high component density. Most of

the buffers are always in off-state. One important design

goal was to attain low off-state quiescent current when no

channel is selected. The low supply current of

±230µA in

off-state and

±4.6mA when one channel is selected, as well

as the reduced

±5V supply voltage, conserves power, simpli-

fies the power supply design, and results in cooler, more

reliable operation.

CIRCUIT LAYOUT

The high-frequency performance of the MPC100 can be

greatly affected by the physical layout of the circuit. The

following tips are offered as suggestions, not as absolutes.

Oscillations, ringing, poor bandwidth and settling, higher

crosstalk, and peaking are all typical problems which plague

high-speed components when they are used incorrectly.

• Bypass power supplies very close to the device pins. Use

tantalum chip capacitors (approximately 2.2

µF), a parallel

470pF ceramic chip capacitor may be added if desired.

Surface-mount types are recommended due to their low

lead inductance.

• PC board traces for signal and power lines should be wide

to reduce impedance or inductance.

• Make short and low inductance traces. The entire physical

circuit layout should be as small as possible.

• Use a low-impedance ground plane on the component side

to ensure that low-impedance ground is available through-

out the layout. Grounded traces between the input traces

are essential to achieve high interchannel crosstalk rejec-

tion. Refer to the suggested layout shown in Figure 6.

• Do not extend the ground plane under high-impedance

nodes sensitive to stray capacitances, such as the buffer’s

input terminals.

• Sockets are not recommended because they add signifi-

cant inductance and parasitic capacitance. If sockets are

required, use zero-profile solderless sockets.

• Use low-inductance and surface-mounted components to

achieve the best AC-performance.

• A resistor (100

Ω to 200Ω) in series with the input of the

buffers may help to reduce peaking. Place the resistor as

close as possible to the pin.

• Plug-in prototype boards and wire-wrap boards will not

function well. A clean layout using RF techniques is

essential.

IN

2

+V

V

OUT

(3)

DB2

(11)

–V

(10)

(12)

(13)

SEL

2

DB1

(14)

(1)

(2)

IN

1

GND

SEL

1

DB3

(9)

(5)

(6)

IN

3

GND

SEL

3

(4)

GND

DB4

(8)

(7)

IN

4

SEL

1

NOTE: DB = Diamond Buffer

FIGURE 2. Simplified Circuit Diagram.