2

SAM0417-051701

ESS Technology, Inc.

ES3210 PRODUCT BRIEF

ES3210 PINOUT

A

ES3210 PINOUT

Figure 1 shows the ES3210 device pinout.

Figure 1 ES3210 Pinout Diagram

ES3210 PIN DESCRIPTION

Table 1 lists the ES3210 pin descriptions.

1

VSS

AUX4

AUX3

AUX2

AUX1

AUX0

PCLK

PCLK2X

CPUCLK

HSYNC

VSYNC

YUV7

YUV6

YUV5

YUV4

YUV3

YUV2

YUV1

YUV0

VDD

VPP

LA12

LA13

LA14

LA15

LA16

LA17

ACLK

AOUT/SEL_PLL0

ATCLK

ATFS/SEL_PLL1

DOE#

AIN

ARCLK

ARFS

TDMCLK

TDMDR

TDMFS

CAS#

VSS

31

30

51

50

80

81

100

2345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

ES3210

100-pin PQFP

Table 1

ES3210 Pin Description

Name

Number

I/O

Definition

VDD

1, 31, 51

I

Voltage supply for 3.3V.

RAS#

2

O

DRAM row address strobe (active low).

DWE#

3

O

DRAM write enable (active low).

MA[8:0]

12:4

O

DRAM multiplexed row and column address bus.

DBUS[15:0]

28:13

I/O

DRAM data bus I/O [15:0].

RESET#

29

I

System reset (active low).

VSS

30, 50, 80, 100

I

Ground.

YUV[7:0]

39:32

O

YUV[7:0] pixel output data.

VSYNC

40

I/O

Vertical sync for screen video interface, programmable for rising or falling edge.

HSYNC

41

I/O

Horizontal sync for screen video interface, programmable for rising or falling edge.

CPUCLK

42

I

RISC and system clock input. CPUCLK is used only if SEL_PLL[1:0] = 00.

PCLK2X

43

I/O

Pixel clock; two times the actual pixel clock for screen video interface.