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LPV802 数据表(PDF) 17 Page - Texas Instruments

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部件名 LPV802
功能描述  TLV8801/TLV8802 320 nA Nanopower Operational Amplifiers for Cost-Optimized Systems
PDF  27 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

LPV802 数据表(HTML) 17 Page - Texas Instruments

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TLV8801, TLV8802
www.ti.com
SNOSD34 – AUGUST 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
8.3 Do's and Don'ts
Do properly bypass the power supplies.
Do add series resistance to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs.
Do add series current limiting resistors and external schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1mA or less (1KΩ per volt).
9 Power Supply Recommendations
The TLV880x is specified for operation from 1.7 V to 5.5 V (±0.75 V to ±2.75 V) over a –40°C to 125°C
temperature range. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 6 V can permanently damage the device.
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines it is
suggested that 100 nF capacitors be placed as close as possible to the operational amplifier power supply pins.
For single supply, place a capacitor between V+ and Vsupply leads. For dual supplies, place one capacitor
between V+ and ground, and one capacitor between Vand ground.
Low bandwidth nanopower devices do not have good high frequency (> 1 kHz) AC PSRR rejection against high-
frequency switching supplies and other 1 kHz and above noise sources, so extra supply filtering is recommended
if kilohertz or above noise is expected on the power supply lines.
10 Layout
10.1 Layout Guidelines
The V+ pin should be bypassed to ground with a low ESR capacitor.
The optimum placement is closest to the V+ and ground pins.
Care should be taken to minimize the loop area formed by the bypass capacitor connection between V+ and
ground.
The ground pin should be connected to the PCB ground plane at the pin of the device.
The feedback components should be placed as close to the device as possible to minimize strays.
10.2 Layout Example
Figure 42. SOT-23 Layout Example (Top View)



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