TNETE2004_09 datasheet(9/47 Pages) TI1

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TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

power interface

TERMINAL

†

NAME

NO.

TYPE†

DESCRIPTION

NAME

120

128

AGND

GND

Ground pin for analog circuitry

AVDD

PWR

VDD pin for analog circuitry

6, 25

8, 31

6, 25

35, 46

8, 31

41, 52

LGND

65, 84

71, 94

GND

Logic ground pin

94, 97

104, 107

104, 115

114, 125

LVDD

30, 41

53, 60

90, 102

120

36, 47

59, 66

100, 112

PWR

Logic VDD pin

RGND0

RGND1

GND

Ground pin for receiver circuitry

RGND2

GND

Ground pin for receiver circuitry

RGND3

RVDD0

RVDD1

RVDD2

RVDD3

PWR

VDD pin for receiver circuitry

TGND0

TGND1

9, 10

21, 22

GND

Ground pin for transmit circuitry

TGND2

TGND3

72, 73

84, 85

GND

Ground pin for transmit circuitry

TVDD0

13, 14

TVDD0

TVDD1

13, 14

25, 26

PWR

VDD pin for transmit circuitry

DD1

TVDD2

76, 77

PWR

VDD pin for transmit circuitry

DD2

TVDD3

88, 89

XGND

GND

Ground pin for crystal-oscillator circuitry

XVDD

PWR

VDD pin for crystal-oscillator circuitry

† GND = ground, PWR = power

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