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TNETE2201BPJW 数据表(PDF) 3 Page - Texas Instruments |
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TNETE2201BPJW 数据表(HTML) 3 Page - Texas Instruments |
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3 / 28 page  TNETE2201B 1.25GIGABIT ETHERNET TRANSCEIVER SLLS367D − JUNE 1999 − REVISED AUGUST 2007 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram LOOPEN TD0 − TD9 10-Bit Register 10 / 10 / Shift Register REFCLK Clock Multiplier 2:1 MUX Synchronous Detect SYNCEN SYNC RD0 − RD9 10-Bit Register 10 / 10 / Shift Register PLL Clock Recovery and Data Retiming ÷ 2 125 MHz 125 MHz 62.5 MHz 62.5 MHz RBC0 RBC1 RX+ RX− TX+ TX− |
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