NRND

TP3404

SNOS703 – DECEMBER 2004

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PIN DESCRIPTIONS

Pin

Pin

Description

No.

Name

1

GNDA

Analog Ground or 0V. All analog signals are referenced to this pin.

15

GNDD

Digital Ground 0V. It must connect to GNDA with a shortest possible trace. This can be done directly underneath the part.

28

VDDA

Positive power supply input to QDASL analog section. It must be 5V ±5%.

16

VDDD

Positive power supply input to QDASL digital section. It must be 5V ±5%, and connect to VDDA with the shortest possible

trace. This can be done directly underneath the part.

11

FS

Frame Sync input: this signal is the 8 kHz clock which defines the start of the transmit and receive frames at the digital

interfaces.

9

MCLK

This pin is the 4.096 MHz Master Clock input, which requires a CMOS logic level clock from a stable source. MCLK must

be synchronous with BCLK.

10

BCLK

Bit Clock logic input, which determines the data shift rate for B and D channel data at the BI, BO, DI and DO pins. BCLK

may be any multiple of 8 kHz from 256 kHz to 4.096 MHz, but must be synchronous with MCLK.

12

BI

Time-division multiplexed input for B1 and B2 channel data to be transmitted to the 4 lines. Data on this pin is shifted in on

the failing edge of BCLK into the B1 and B2 channels during the selected transmit time-slots.

13

BO

Time-division multiplexed receive data output bus. B1 and B2 channel data from all 4 lines is shifted out on the rising edge

of BCLK on this pin during the assigned receive time-slots. At all other times this output is TRI-STATE (high impedance).

14

TSB

This pin is an open-drain output which is normally high impedance but pulls low during any active B channel receive time

slots at the BO pin.

7

DI

Time-division multiplexed input for D channel data to be transmitted to the 4 lines. Data on this pin is shifted in on the

failing edge of BCLK into the D channel during the selected transmit sub-time-slots.

8

DO

Time-division multiplexed output for D channel data received from the 4 lines. Data on this pin is shifted out on the rising

edge of BCLK during the selected receive sub-time-slot.

19

CCLK

Microwire Control Clock input. This clock shifts serial control information into CI and out from CO when the CS input is low,

depending on the current instruction. CCLK may be asynchronous with the other system clocks.

21

CI

Control data Input. Serial control information is shifted into the QDASL on this pin on the rising edges of CCLK when CS is

low.

17

INT

Interrupt request output, a latched output signal which is normally high impedance and goes low to indicate a change of

status of any of the 4 loop transmission systems. This latch is cleared when the Status Register is read by the

microprocessor. Bipolar Violation does not effect this output.

20

CO

Control data Output. Serial control/status information is shifted out from the QDASL on this pin on the falling edges of

CCLK when CS is low.

18

CS

Chip Select input. When this pin is pulled low, the Microwire interface is enabled to allow control information to be written

in to and out from the device via the CI and CO ins. When high, this pin inhibits the Microwire interface.

4

Lo0

Line driver transmit outputs for the 4 transmission channels. Each output is an amplifier intended to drive a transformer.

3

Lo1

26

Lo2

25

Lo3

5

Li0

Line receive amplifier inputs for the 4 transmission channels. Each Li pin is a self-biased high impedance input which

2

Li1

should be connected to the transformer via the recommended line interface circuit.

27

Li2

24

Li3

4

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