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LP2997 数据表(PDF) 10 Page - National Semiconductor (TI) |
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LP2997 数据表(HTML) 10 Page - National Semiconductor (TI) |
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10 / 12 page ![]() Typical Application Circuits Several different application circuits have been shown to illustrate some of the options that are possible in configuring the LP2997. Graphs of the individual circuit performance can be found in the Typical Performance Characteristics section in the beginning of the datasheet. These curves illustrate how the maximum output current is affected by changes in AVIN and PVIN. Figure 2 shows the recommended circuit configuration for DDR-II applications. The output stage is connected to the 1.8V rail and the AVIN pin can be connected to either a 2.5V, 3.3V or 5V rail. This circuit permits termination in a minimum amount of board space and component count. Capacitor selection can be varied depending on the number of lines terminated and the maximum load transient. However, with motherboards and other applications where V TT is distributed across a long plane it is advisable to use multiple bulk capacitors and addition to high frequency decoupling. The bulk output ca- pacitors should be situated at both ends of the V TT plane for optimal placement. Large aluminum electrolytic capacitors are used for their low ESR and low cost. PCB Layout Considerations 1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin. 2. V SENSE should be connected to the VTT termination bus at the point where regulation is required. For mother- board applications an ideal location would be at the center of the termination bus. 3. V DDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the most accurate point for creating the reference voltage. 4. For improved thermal performance excessive top side copper should be used to dissipate heat from the pack- age. Numerous vias from the ground connection to the internal ground plane will help. Additionally these can be located underneath the package if manufacturing stan- dards permit. 5. Care should be taken when routing the V SENSE trace to avoid noise pickup from switching I/O signals. A 0.1uF ceramic capacitor located close to the SENSE can also be used to filter any unwanted high frequency signal. This can be an issue especially if long SENSE traces are used. 6. V REF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This ca- pacitor should be located as close as possible to the V REF pin. 20109413 FIGURE 2. Recommended DDR-II Termination www.national.com 10 |
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