This output remains active during the shutdown state and

thermal shutdown events for the suspend to RAM function-

ality.

V

TT

V

resistors. It is capable of sinking and sourcing current while

regulating the output precisely to VDDQ / 2. The LP2997 is

designed to handle continuous currents of up to +/- 0.5A with

excellent load regulation. If a transient is expected to last

above the maximum continuous current rating for a signifi-

cant amount of time, then the bulk output capacitor should

be sized large enough to prevent an excessive voltage drop.

If the LP2997 is to operate in elevated temperatures for long

durations care should be taken to ensure that the maximum

junction temperature is not exceeded. Proper thermal de-

rating should always be used. (Please refer to the Thermal

Dissipation section) If the junction temperature exceeds the

thermal shutdown point than V

returns below the temperature hysteresis trip-point

Component Selection

INPUT CAPACITOR

The LP2997 does not require a capacitor for input stability,

but it is recommended for improved performance during

large load transients to prevent the input rail from dropping.

The input capacitor should be located as close as possible to

the PVIN pin. Several recommendations exist dependent on

the application required. A typical value recommended for AL

electrolytic capacitors is 22 µF. Ceramic capacitors can also

be used. A value in the range of 10 µF with X5R or better

would be an ideal choice. The input capacitance can be

reduced if the LP2997 is placed close to the bulk capaci-

tance from the output of the 1.8V DC-DC converter. For the

AVIN pin, a small 0.1uF ceramic capacitor is sufficient to

prevent excessive noise from coupling into the device.

OUTPUT CAPACITOR

The LP2997 has been designed to be insensitive of output

capacitor size or ESR (Equivalent Series Resistance). This

allows the flexibility to use any capacitor desired. The choice

for output capacitor will be determined solely on the applica-

tion and the requirements for load transient response of V

As a general recommendation the output capacitor should

be sized above 100 µF with a low ESR for SSTL applications

with DDR-SDRAM. The value of ESR should be determined

by the maximum current spikes expected and the extent at

which the output voltage is allowed to droop. Several capaci-

tor options are available on the market and a few of these

are highlighted below:

AL - It should be noted that many aluminum electrolytics only

specify impedance at a frequency of 120 Hz, which indicates

they have poor high frequency performance. Only aluminum

electrolytics that have an impedance specified at a higher

frequency (100 kHz) should be used for the LP2997. To

improve the ESR several AL electrolytics can be combined in

parallel for an overall reduction. An important note to be

aware of is the extent at which the ESR will change over

temperature. Aluminum electrolytic capacitors can have their

ESR rapidly increase at cold temperatures.

Ceramic - Ceramic capacitors typically have a low capaci-

tance, in the range of 10 to 100 µF range, but they have

excellent AC performance for bypassing noise because of

very low ESR (typically less than 10 m

Ω). However, some

dielectric types do not have good capacitance characteris-

tics as a function of voltage and temperature. Because of the

typically low value of capacitance it is recommended to use

ceramic capacitors in parallel with another capacitor such as

an aluminum electrolytic. A dielectric of X5R or better is

recommended for all ceramic capacitors.

Hybrid - Several hybrid capacitors such as OS-CON and SP

are available from several manufacturers. These offer a

large capacitance while maintaining a low ESR. These are

the best solution when size and performance are critical,

although their cost is typically higher than any other capaci-

tors.

Thermal Dissipation

Since the LP2997 is a linear regulator any current flow from

V

To prevent damaging the part from exceeding the maximum

allowable junction temperature, care should be taken to

derate the part dependent on the maximum expected ambi-

ent temperature and power dissipation. The maximum allow-

able internal temperature rise (T

given the maximum ambient temperature (T

application and the maximum allowable junction temperature

(T

T

From this equation, the maximum power dissipation (P

of the part can be calculated:

P

θ

JA

The

θ

ables: the package used; the thickness of copper; the num-

ber of vias and the airflow. For instance, the

θ

is 163˚C/W with the package mounted to a standard 8x4

2-layer board with 1oz. copper, no airflow, and 0.5W dissi-

pation at room temperature. This value can be reduced to

151.2˚C/W by changing to a 3x4 board with 2 oz. copper that

is the JEDEC standard. Figure 1 shows how the

θ

with airflow for the two boards mentioned.

Additional improvements can be made by the judicious use

of vias to connect the part and dissipate heat to an internal

ground plane. Using larger traces and more copper on the

20109407

FIGURE 1.

θ

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