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MAX3535ECWI 数据表(PDF) 23 Page - Maxim Integrated Products |
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MAX3535ECWI 数据表(HTML) 23 Page - Maxim Integrated Products |
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23 / 25 page ![]() +3V to +5V, 2500VRMS Isolated RS-485/RS-422 Transceivers with ±15kV ESD Protection ______________________________________________________________________________________ 23 Machine Model The Machine Model for ESD tests all pins using a 200pF storage capacitor and zero discharge resis- tance. Its objective is to simulate the stress caused by contact that occurs with handling and assembly during manufacturing. All pins require this protection during manufacturing, not just inputs and outputs. Therefore, after PC board assembly, the Machine Model is less relevant to I/O ports. Skew The self-oscillation circuit shown in Figure 5 is an excel- lent way to get an approximate measure of the speed of the MAX3535E/MXL1535E. An oscillation frequency of 250kHz in this configuration implies a data rate of at least 500kbps for the receiver and transmitter com- bined. In practice, data can usually be sent and received at a considerably higher data rate, normally limited by the allowable jitter and data skew. If the sys- tem can tolerate a 25% data skew, (the difference between tPLH1 and tPHL1), the 285ns maximum jitter specification implies a data rate of 877kbps. Lower data rates result in less distortion and jitter (Figure 16). Higher rates are possible but with more distortion and jitter. The data rate should always be limited below 1.75Mbps for both receiver and driver to avoid interfer- ence with the internal barrier communication. Layout Considerations The MAX3535E/MXL1535E pin configurations enable optimal PC board layout by minimizing interconnection lengths and crossovers: • For maximum isolation, the isolation barrier should not be breached except by the MAX3535E/MXL1535E and the transformer. Connections and components from one side of the barrier should not be located near those of the other side of barrier. •A shield trace connected to the ground on each side of the barrier can help intercept capacitive currents that might otherwise couple into the DI and SOL inputs. In a double-sided or multilayer board, these shield traces should be present on all conductor layers. • Try to maximize the width of the isolation barrier wherever possible. A clear space of at least 0.25in between GND1 and GND2 is recommended. IP 100% 90% 36.8% tRL TIME tDL CURRENT WAVEFORM PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) Ir 10% 0 0 AMPERES Figure 15. Human Body Current Waveform 0 10 5 20 15 30 25 35 45 40 50 0 500 750 250 1000 1250 1500 1750 2000 DATA SKEW vs. DATA RATE DATA RATE (kbps) TYP SKEW MAX SKEW Figure 16. Data Skew vs. Data Rate Graph |
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