Via

TPD3S044

TPD4E05U06

D-

D+

GND

SSRX-

GND

SSTX-

SSRX+

SSTX+

GND

GND

EN GND

IN

OUT

D1

D2

D1+

D1-

D2+

D2-

GND

GND

Top Layer GND Plane

TPD3S014, TPD3S044

www.ti.com

SLVSCP4B – OCTOBER 2014 – REVISED AUGUST 2015

Layout Examples (continued)

Figure 37. USB3.0 Type A TPD3S044 Board Layout

11.3 Power Dissipation and Junction Temperature

It is good design practice to estimate power dissipation and maximum expected junction temperature of the

TPD3S0x4s. The system designer can control choices of the devices proximity to other power dissipating

devices and printed circuit board (PCB) design based on these calculations. These have a direct influence on

maximum junction temperature. Other factors, such as airflow and maximum ambient temperature, are often

determined by system considerations. It is important to remember that these calculations do not include the

effects of adjacent heat sources, and enhanced or restricted air flow. Addition of extra PCB copper area around

these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low

as practical. In particular, connect the GND pin to a large ground plane for the best thermal dissipation. The

the Thermal Information table. It is based on the use of the JEDEC high-k circuit board construction with 4, 1 oz.

copper weight layers (2 signal and 2 plane).

Copyright © 2014–2015, Texas Instruments Incorporated

Submit Documentation Feedback

21

Product Folder Links: TPD3S014 TPD3S044