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ISO7841FDWWR 数据表(PDF) 21 Page - Texas Instruments |
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ISO7841FDWWR 数据表(HTML) 21 Page - Texas Instruments |
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21 / 37 page ![]() Input (Device Without Suffix F) Output Enable OUTx VCCO ~20 W INx 1.5 MW 985 W Input (Device With Suffix F) VCCI VCCI VCCI INx 1.5 MW 985 W VCCI VCCI VCCI VCCI Enx 2 MW 1970 W VCCO VCCO VCCO VCCO Copyright © 2016, Texas Instruments Incorporated 21 ISO7841, ISO7841F www.ti.com SLLSEM3F – NOVEMBER 2014 – REVISED APRIL 2016 Product Folder Links: ISO7841 ISO7841F Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated (1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level ; Z = High Impedance (2) A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output. (3) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V. 8.4 Device Functional Modes Table 7 lists the ISO7841 functional modes. Table 7. Function Table(1) VCCI VCCO INPUT (INx)(2) OUTPUT ENABLE (ENx) OUTPUT (OUTx) COMMENTS PU PU H H or open H Normal Operation: A channel output assumes the logic state of its input. L H or open L Open H or open Default Default mode: When INx is open, the corresponding channel output goes to its default logic state. Default= High for ISO7841 and Low for ISO7841F. X PU X L Z A low value of Output Enable causes the outputs to be high-impedance PD PU X H or open Default Default mode: When VCCI is unpowered, a channel output assumes the logic state based on the selected default option. Default= High for ISO7841 and Low for ISO7841F. When VCCI transitions from unpowered to powered-up, a channel output assumes the logic state of its input. When VCCI transitions from powered-up to unpowered, channel output assumes the selected default state. X PD X X Undetermined When VCCO is unpowered, a channel output is undetermined (3). When VCCO transitions from unpowered to powered-up, a channel output assumes the logic state of its input 8.4.1 Device I/O Schematics Figure 17. Device I/O Schematics |
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