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DAC5571IDBVT 数据表(PDF) 18 Page - Texas Instruments |
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DAC5571IDBVT 数据表(HTML) 18 Page - Texas Instruments |
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18 / 21 page ![]() www.ti.com POWER-ON RESET POWER-DOWN MODES Resistor String DAC Power-Down VOUT Amplifier Resistor Network Circuitry CURRENT CONSUMPTION DRIVING RESISTIVE AND CAPACITIVE LOADS DAC5571 SLAS405 – DECEMBER 2003 The DAC5571 contains a power-on reset circuit that controls the output voltage during power up. On power up, the DAC register is filled with zeros and the output voltage is 0 V. It remains at a zero-code output until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the DAC output while it is in the process of powering up. The DAC5571 contains four separate modes of operation. These modes are programmable via two bits (PD1 and PD0). Table 1 shows how the state of these bits correspond to the mode of operation. Table 1. Modes of Operation for the DAC5571 PD1 PD0 OPERATING MODE 0 0 Normal Operation 0 1 1k Ω to AGND, PWD 1 0 100 k Ω to AGND, PWD 1 1 High Impedance, PWD When both bits are set to zero, the device works normally with normal power consumption of 150 µA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while in power-down mode. There are three different options: The output is connected internally to AGND through a 1-k Ω resistor, a 100-kΩ resistor, or it is left open-circuited (high impedance). The output stage is illustrated in Figure 46. Figure 46. Output Stage During Power Down All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power down. The time required to exit power down is typically 2.5 µs for AVDD = 5 V and 5 µs for AVDD = 3 V. See the Typical Characteristics section for more information. The DAC5571 typically consumes 150 µA at VDD = 5 V and 120 µA at VDD = 3 V. Additional current consumption can occur due to the digital inputs if VIH << VDD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In power-down mode, typical current consumption is 200 nA. The DAC5571 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset and gain error margins, the DAC5571 can operate rail-to-rail when driving a capacitive load. When the outputs of the DAC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This may occur within approximately the top 20 mV of the DAC's digital input-to-voltage output transfer characteristic. 18 |
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