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ICS8312AYLF 数据表(PDF) 1 Page - Integrated Circuit Systems |
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ICS8312AYLF 数据表(HTML) 1 Page - Integrated Circuit Systems |
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1 / 12 page ![]() 8312AY http://www.icst.com/products/hiperclocks.html REV. C JUNE 14, 2004 1 Integrated Circuit Systems, Inc. ICS8312 LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER GENERAL DESCRIPTION The ICS8312 is a low skew, 1-to-12 LVCMOS / LVTTL Fanout Buffer and a member of the HiPerClockS™family of High Performance Clock Solutions from ICS. The ICS8312 single ended clock input accepts LVCMOS or LVTTL input lev- els. The low impedance LVCMOS outputs are designed to drive 50 Ω series or parallel terminated transmission lines.The effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines. The ICS8312 is characterized at full 3.3V, 2.5V, and 1.8V, mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply modes. Guaranteed output and part-to-part skew char- acteristics along with the 1.8V output capabilities makes the ICS8312 ideal for high performance, single ended applica- tions that also require a limited output voltage. BLOCK DIAGRAM PIN ASSIGNMENT FEATURES • 12 LVCMOS / LVTTL outputs • LVCMOS / LVTTL clock input • Maximum output frequency: 250MHz • Output skew: 150ps (maximum) • Operating supply modes: Core/Output 3.3V/3.3V, 2.5V/2.5V, 1.8V/1.8V, 3.3V/2.5V, 3.3V/1.8V, 2.5V/1.8V • 0°C to 85°C ambient operating temperature • Lead-Free package available • Industrial temperature information available upon request HiPerClockS™ ICS 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 Q4 VDDO Q5 GND Q6 VDDO Q7 GND GND VDD CLK_EN CLK GND OE VDD GND ICS8312 32-Lead LQFP 7mm x 7mm x 1.4mm body package Y Pacakge Top View Q0:Q11 CLK_EN CLK OE nD Q LE 12 |
类似零件编号 - ICS8312AYLF |
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类似说明 - ICS8312AYLF |
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