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DS90CF563 数据表(PDF) 4 Page - National Semiconductor (TI) |
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DS90CF563 数据表(HTML) 4 Page - National Semiconductor (TI) |
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4 / 12 page  Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units TRANSMITTER SUPPLY CURRENT I CCTZ Transmitter Supply Current, Power Down Power Down = Low 125 µA RECEIVER SUPPLY CURRENT I CCRW Receiver Supply Current, C L = 8 pF, f = 32.5 MHz 64 77 mA Worst Case Worst Case Pattern f = 37.5 MHz 70 85 mA ( Figure 1, Figure 4)f = 65 MHz 110 140 mA I CCRG Receiver Supply Current, C L = 8 pF, f = 32.5 MHz 35 55 mA 16 Grayscale 16 Grayscale Pattern f = 37.5 MHz 37 55 mA ( Figure 2, Figure 4)f = 65 MHz 55 67 mA I CCRZ Receiver Supply Current, Power Down = Low 110 µA Power Down Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VCC = 5.0V and TA = +25˚C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci- fied (except VOD and ∆V OD). Note 4: ESD Rating: HBM (1.5 k Ω, 100 pF) PLL V CC ≥ 1000V All other pins ≥ 2000V EIAJ (0 Ω, 200 pF) ≥ 150V Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time ( Figure 3) 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time ( Figure 3) 0.75 1.5 ns TCIT TxCLK IN Transition Time ( Figure 5)8 ns TCCS TxOUT Channel-to-Channel Skew (Note 5) ( Figure 6) 350 ps TCCD TxCLK IN to TxCLK OUT Delay @ 25˚C, V CC = 5.0V 3.5 8.5 ns ( Figure 9) TCIP TxCLK IN Period ( Figure 7) 15 T 50 ns TCIH TxCLK IN High Time ( Figure 7) 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time ( Figure 7) 0.35T 0.5T 0.65T ns TSTC TxIN Setup to TxCLK IN ( Figure 7 )f = 65 MHz 5 3.5 ns THTC TxIN Hold to TxCLK IN ( Figure 7) 2.5 1.5 ns TPDD Transmitter Powerdown Delay ( Figure 18) 100 ns TPLLS Transmitter Phase Lock Loop Set ( Figure 11)10 ms TPPos0 Transmitter Output Pulse Position 0 ( Figure 13) −0.30 0 0.30 ns TPPos1 Transmitter Output Pulse Position 1 1.70 1/7 T clk 2.50 ns TPPos2 Transmitter Output Pulse Position 2 3.60 2/7 T clk 4.50 ns TPPos3 Transmitter Output Pulse Position 3 5.90 3/7 T clk 6.75 ns TPPos4 Transmitter Output Pulse Position 4 8.30 4/7 T clk 9.00 ns TPPos5 Transmitter Output Pulse Position 5 10.40 5/7 T clk 11.10 ns TPPos6 Transmitter Output Pulse Position 6 12.70 6/7 T clk 13.40 ns Note 5: This limit based on bench characterization. www.national.com 4 |
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